MPC8280 datasheet(129/1386 Pages) FREESCALE

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G2_LE Core

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

2-13

ILOCK

Instruction cache lock

0 Normal operation

1 Instruction cache is locked. A locked cache supplies data normally on a hit, but an access is

treated as a cache-inhibited transaction on a miss. On a miss, the transaction to the bus is

single-beat, however, CI still reflects the original state as determined by address translation

independent of cache locked or disabled status.

To prevent locking during a cache access, an isync must precede the setting of ILOCK.

DLOCK

Data cache lock

0 Normal operation

1 Data cache is locked. A locked cache supplies data normally on a hit but an access is treated

as a cache-inhibited transaction on a miss. On a miss, the transaction to the bus is single-beat,

however, CI still reflects the original state as determined by address translation independent

of cache locked or disabled status. A snoop hit to a locked L1 data cache performs as if the

cache were not locked. A cache block invalidated by a snoop remains invalid until the cache is

unlocked.

To prevent locking during a cache access, a sync must precede the setting of DLOCK.

ICFI

Instruction cache flash invalidate 2

0 The instruction cache is not invalidated. The bit is cleared when the invalidation operation

begins (usually the next cycle after the write operation to the register). The instruction cache

must be enabled for the invalidation to occur.

1 An invalidate operation is issued that marks the state of each instruction cache block as invalid

without writing back modified cache blocks to memory. Cache access is blocked during this

time. Bus accesses to the cache are signaled as a miss during invalidate-all operations. Setting

ICFI clears all the valid bits of the blocks and the PLRU bits to point to way L0 of each set. Once

the L1 flash invalidate bits are set through an mtspr instruction, hardware automatically resets

these bits in the next cycle (provided that the corresponding cache enable bits are set in HID0).

DCFI

Data cache flash invalidate 2

0 The data cache is not invalidated. The bit is cleared when the invalidation operation begins

(usually the next cycle after the write operation to the register). The data cache must be

enabled for the invalidation to occur.

1 An invalidate operation is issued that marks the state of each data cache block as invalid

without writing back modified cache blocks to memory. Cache access is blocked during this

time. Bus accesses to the cache are signaled as a miss during invalidate-all operations. Setting

DCFI clears all the valid bits of the blocks and the PLRU bits to point to way L0 of each set.

Once the L1 flash invalidate bits are set through an mtspr instruction, hardware automatically

resets these bits in the next cycle (provided that the corresponding cache enable bits are set

in HID0).

22–23

—

Reserved

IFEM

Enable M bit on 60x bus for instruction fetches

0 M bit not reflected on 60x bus. Instruction fetches are treated as nonglobal on the bus.

1 Instruction fetches reflect the M bit from the WIM settings on the 60x bus.

25–26

—

Reserved

FBIOB

Force branch indirect on bus.

0 Register indirect branch targets are fetched normally

1 Forces register indirect branch targets to be fetched externally.

ABE

Address broadcast enable

dcbf, dcbi, and dcbst instructions are not broadcast on the 60x bus.

dcbf, dcbi, and dcbst generate address-only broadcast operations on the 60x bus.

Table 2-1. HID0 Field Descriptions (continued)

Bits

Name

Description

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