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MPC8280 датащи(PDF) 280 Page - Freescale Semiconductor, Inc

номер детали MPC8280
подробное описание детали  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 датащи(HTML) 280 Page - Freescale Semiconductor, Inc

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The 60x Bus
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
8-4
Freescale Semiconductor
Figure 8-2. 60x-Compatible Bus Mode
8.3
60x Bus Protocol Overview
Typically, 60x bus accesses consist of address and data tenures, which in turn each consist of three
phases—arbitration, transfer, and termination, as shown in Figure 8-3.. The independence of the tenures is
indicated by showing the data tenure overlap the next address tenure, which allows split-bus transactions
to be implemented at the system level in multiprocessor systems. Figure 8-3 shows a data transfer that
consists of a single-beat transfer of as many as 256 bits. Four-beat burst transfers of 32-byte cache blocks
require data transfer termination signals for each beat of data. Note that the MPC8280 supports port sizes
of 8, 16, 32, and 64 bits and requires the additional bus signal, PSDVAL, which is not defined by the 60x
BR
BG
TS
A[0–31]
TT[0–4]
TSIZ[0–3]
TBST
CI
WT
GBL
AACK
ARTRY
DBG
D[0–63]
DP[0–7]
TA
TEA
MPC8280
I/O
MEM
External Device
BR
BG
DBG
Latch
Latch &
DRAM MUX
Memory Control Signals
AP[0–3]
TS
APE



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