MPC8280 datasheet(284/1386 Pages) FREESCALE

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The 60x Bus

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

8-8

Freescale Semiconductor

asserted; if BR is not asserted (no pending request), it negates BG and asserts the parked bus grant

(BG_INT in this example).

The master can assert BR and receive a qualified bus grant without subsequently using the bus. It can

negate (cancel) BR before accepting a qualified bus grant. This can occur when a replacement copyback

transaction waiting to be run on the bus is killed by a snoop of another bus master. This can also occur

when the reservation set by a pending stwcx. transaction is cancelled by a snoop of another master. In both

cases, the pending transaction by the processor is cancelled and BR is negated.

Figure 8-4. Address Bus Arbitration with External Bus Master

8.4.2

Address Pipelining

The MPC8280 supports one-level address pipelining by asserting AACK to the current bus master when

its data tenure starts and by granting the address bus to the next requesting device before the current data

bus tenure completes. Address pipelining improves data throughput by allowing the memory-control

hardware to decode a new set of address and control signals while the current data transaction finishes.

The MPC8280 pipelines data bus operations in strict order with the associated address operations.

Figure 8-5 shows how address pipelining allows address tenures to overlap the associated data tenures.

CLKOUT

BR INT

BG INT

MPC8280

ABB

ADDR+

MPC8280

External

AACK

ARTRY

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