MPC8280 datasheet(283/1386 Pages) FREESCALE

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The 60x Bus

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

8-7

master before the current data bus tenure has completed. Two address tenures can occur before the current

data bus tenure completes. The MPC8280 also supports non-pipelined accesses.

8.4

Address Tenure Operations

This section describes the three phases of the address tenure—address bus arbitration, address transfer, and

address termination.

8.4.1

Address Arbitration

Bus arbitration can be handled either by an external arbiter or by the internal on-chip arbiter. The

arbitration configuration (external or internal) is chosen at system reset. For internal arbitration, the

MPC8280 provides arbitration for the 60x address bus and the system is optimized for three external bus

masters besides the MPC8280. The bus request (BR) for the external device is an external input to the

arbiter. The bus grant signal for the external device (BG) is output to the external device.The BG signal

asserted by MPC8280’s on-chip arbiter is asserted one clock after the current master on the bus has

asserted AACK; therefore, it can be called a qualified BG. Assuming that all potential masters negate ABB

one clock after receiving AACK, the device receiving BG can start the address tenure (by asserting TS)

one clock after receiving BG. In addition to the external signals, there are internal request and grant signals

for the MPC8280 processor, communications processor, refresh controller, and the PCI internal bridge.

Bus accesses are prioritized, with programmable priority. When a MPC8280’s internal master needs the

60x bus, it asserts the internal bus request along with the request level. The arbiter asserts the internal bus

grant for the highest priority request.

The MPC8280 supports address bus parking through the use of the parked master bits in the arbiter

configuration register. The MPC8280 parks the address bus (asserts the address bus grant signal in

anticipation of an address bus request) to the external master or internal masters. When a device is parked,

the arbiter can hold BG asserted for a device even if that device has not requested the bus. Therefore, when

the parked device needs to perform a bus transaction, it skips the bus request delay and assumes address

bus mastership on the next cycle. For this case, BR is not asserted and the access latency seen by the device

is shortened by one cycle.

The MPC8280 and external device bus devices qualify BG by sampling ARTRY in the negated state prior

to taking address bus mastership. The negation of ARTRY during the address retry window (one cycle after

the assertion of AACK) indicates that no address retry is requested. If a device detects ARTRY asserted,

it cannot accept a address bus grant during the ARTRY cycle or the cycle following. A device that asserts

ARTRY due to a modified cache block hit, for example, asserts its bus request during the cycle after the

assertion of ARTRY and assumes bus mastership for the cache block push when it is given a bus grant.

The series of address transfers in Figure 8-4 shows the transfer protocol when the MPC8280 is configured

in 60x-compatible bus mode. In this example, MPC8280 is initially parked on the bus with BG

INT-asserted (note that BG INT is an internal signal not seen by the user at the pins), which lets it start an

address bus tenure by asserting TS. During the same clock cycle, the external master’s bus request is

asserted to request access to the 60x bus, thereby causing the negation of BG INT internally and the

assertion of BG at the pin. Following MPC8280’s address tenure, the external master takes the bus and

initiates its address transaction. The on-chip arbiter samples BR during the clock cycle in which AACK is

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