MPC8280 datasheet(277/1386 Pages) FREESCALE

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MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

8-1

Chapter 8

The 60x Bus

The 60x bus, which is used by processors that implement the PowerPC architecture, provides flexible

support for the on-chip MPC603 processor as well as other internal and external bus devices. The 60x bus

supports 32-bit addressing, a 64-bit data bus, and burst operations that transfer as many as 256 bits of data

in a four-beat burst. The 60x data bus can be accessed in 8-, 16-, 32-, and 64-bit data ports. The 60x bus

supports accesses of 1, 2, 3, and 4 bytes, aligned or unaligned, on 4-byte (word) boundaries; it also supports

64-, 128-, 192-, and 256-bit accesses.

The address and data buses support synchronous, one-level pipeline transactions. The 60x bus interface

can be configured to support both external and internal masters or internal masters only.

8.1

Terminology

Table 8-1 defines terms used in this chapter.

Table 8-1. Terminology

Term

Definition

Atomic

A bus access that attempts to be part of a read-write operation to the same address uninterrupted

by any other access to that address. The MPC8280 initiates the read and write separately, but

signals the memory system that it is attempting an atomic operation. If the operation fails, status is

kept so that MPC8280 can try again.

Beat

A single state on the MPC8280 interface that may extend across multiple bus cycles. (An MPC8280

transaction can be composed of multiple address or data beats.)

Burst

A multiple-beat data transfer whose total size is typically equal to a cache block size (in MPC8280:

32 bytes, or 4 data beats at 8 bytes per beat).

Cache block

The PowerPC architecture defines the basic unit of coherency as a cache block, which can be

considered the same thing as a cache line.

Clean

An operation that causes a cache block to be written to memory if modified, and then left in a valid,

unmodified state in the cache.

Flush

An operation that causes a cache block to be invalidated in the cache, and its data, if modified, to

be written back to main memory.

Kill

An operation that causes a cache block to be invalidated in the cache without writing any modified

data to memory.

Lane

A sub-grouping of signals within a bus. An 8-bit section of the address or data bus may be referred

to as a byte lane for that bus.

Master

The device that owns the address or data bus, the device that initiates or requests the transaction.

Modified

Identifies a cache block The M state in a MESI or MEI protocol.

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