MPC8280 datasheet(249/1386 Pages) FREESCALE

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External Signals

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

6-7

L2_HIT

IRQ4

L2 cache hit—(Input) It is used for L2 cache control. Assertion of this pin indicates that the 60x

transaction will be handled by the L2 cache. In this case, the memory controller will not start an

access to the memory it controls.

Interrupt request 4—This input is one of the eight external lines that can request (by means of the

internal interrupt controller) a service routine from the core.

CPU_BG

BADDR31

IRQ5

CINT

CPU bus grant—(Output) The value of the 60x core bus grant is driven on this pin to be used by

an external MPC2605GA L2 cache. The driven bus grant is not qualified; that is, when using an

external arbiter, the user should qualify this signal with the bus grant input to the MPC8280 before

connecting it to the L2 cache.

Burst address 31—There are five burst address output of the 60x memory controller used in an

external master configuration and are connected directly to the memory devices controlled by

MPC8280’s memory controller. For information on the use of this signal, see Section 11.2.14,

“BADDR[27:31] Signal Connections.”

Interrupt Request 5—This input is one of the eight external lines that can request (by means of

the internal interrupt controller) a service routine from the core.

Critical interrupt—Critical interrupt input to the core

CPU_DBG

CPU data bus grant—(Output) Valid only when using the internal arbiter (PPC_ACR[EARB] = 0).

The OR of all data bus grant signals for internal masters from the internal arbiter is driven on

CPU_DBG. CPU_DBG should be connected to the CPU DBG input of an external MPC2605GA

L2 cache. (If an external arbiter is used, the CPU DBG input of the external MPC2605GA L2

cache should be connected to the DBG driven from the external arbiter to this MPC8280.)

CPU_BR

CPU bus request—(Output) The value of the 60x core bus request is driven on this pin for the use

of an external L2 cache.

CS[0–9]

Chip select—These are output pins that enable specific memory devices or peripherals

connected to MPC8280 buses.

CS[10]

BCTL1

Chip select—These are output pins that enable specific memory devices or peripherals

connected to MPC8280 buses.

Buffer control 1—Output signal whose function is controlling buffers on the 60x data bus. Usually

used with BCTL0. The exact function of this pin is defined by the value of SIUMCR[BCTLC]. See

Section 4.3.2.6, “SIU Module Configuration Register (SIUMCR),” for details.

CS[11]

AP[0]

Chip select—Output that enable specific memory devices or peripherals connected to MPC8280

buses.

Address parity 0—(Input/output) The 60x master that drives the address bus, drives also the

address parity signals. The value driven on address parity 0 pin should give odd parity (odd

number of ‘1’s) on the group of signals that includes address parity 0 and A[0–7].

BADDR[27–28]

Burst address 27–28—There are five burst address output pins. These pins are outputs of the

60x memory controller. Used in external master configuration and connected directly to the

memory devices controlled by MPC8280’s memory controller. For information on the use of these

signals, see Section 11.2.14, “BADDR[27:31] Signal Connections.”

ALE

Address latch enable—This output pin controls the external address latch that should be used in

external master 60x bus configuration.

Table 6-1. External Signals (continued)

Signal

Description

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