MPC8280 datasheet(246/1386 Pages) FREESCALE

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External Signals

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

6-4

Freescale Semiconductor

DBB

IRQ3

60x data bus busy—(Input/output) As an output the MPC8280 asserts this pin for the duration of

the data bus tenure. Following a TA, which terminates the data bus tenure, the MPC8280 negates

DBB for a fraction of a bus cycle and than stops driving this pin. As an input, the MPC8280 does

not assume 60x data bus ownership as long as it senses DBB asserted by an external 60x bus

master.

Interrupt request 3—This input is one of the eight external lines that can request (by means of the

internal interrupt controller) a service routine from the core.

D[0–63]

60x data bus—These are input/output pins. In write transactions the 60x bus master drives the

valid data on this bus. In read transactions the 60x slave drives the valid data on this bus.

DP[0]

RSRV

EXT_BR2

60x data parity 0—(Input/output) The 60x agent that drives the data bus drives also the data parity

signals. The value driven on data parity 0 pin should give odd parity (odd number of 1’s) on the

group of signals that includes data parity 0 and D[0–7].

Reservation—The value driven on this output pin represents the state of the coherency bit in the

reservation address register that is used by the lwarx and stwcx. instructions.

External bus request 2—(Input). An external master should assert this pin to request 60x bus

ownership from the internal arbiter.

IRQ1

DP[1]

EXT_BG2

Interrupt request 1—This input is one of the eight external lines that can request (by means of the

internal interrupt controller) a service routine from the core.

60x data parity 1—(Input/output) The 60x agent that drives the data bus drives also the data parity

signals. The value driven on data parity 1 pin should give odd parity (odd number of ‘1’s) on the

group of signals that includes data parity 1 and D[8–15].

External bus grant 2—(Output) The MPC8280 asserts this pin to grant 60x bus ownership to an

external bus master.

IRQ2

DP[2]

TLBISYNC

EXT_DBG2

Interrupt request 2—This input is one of the eight external lines that can request (by means of the

internal interrupt controller) a service routine from the core.

60x data parity 2—(Input/output) The 60x agent that drives the data bus drives also the data parity

signals. The value driven on data parity 2 pin should give odd parity (odd number of ‘1’s) on the

group of signals that includes data parity 2 and S[16–23].

TLB sync—This input pin can be used to synchronize 60x core instruction execution to hardware

indications. Asserting this pin will force the core to stop instruction execution following a tlbsync

instruction execution. The core resumes instructions execution once this pin is negated.

External data bus grant 2—(Output) The MPC8280 asserts this pin to grant 60x data bus

ownership to an external bus master.

Table 6-1. External Signals (continued)

Signal

Description

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