MPC8280 datasheet(248/1386 Pages) FREESCALE

248 / 1386 page

External Signals

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

6-6

Freescale Semiconductor

PSDVAL

60x data valid—(Input/output) Assertion of the PSDVAL pin indicates that a data beat is valid on

the data bus. The difference between the TA pin and the PSDVAL pin is that the TA pin is asserted

to indicate 60x data transfer terminations while the PSDVAL signal is asserted with each data

beat movement. Thus always when TA is asserted, PSDVAL will be asserted but when PSDVAL

is asserted, TA is not necessarily asserted. For example when a double word (2x64 bits) transfer

is initiated by the SDMA to a memory device that has 32 bits port size, PSDVAL will be asserted

3 times without TA and finally both pins will be asserted to terminate the transfer.

Transfer acknowledge—(Input/output) Indicates that a 60x data beat is valid on the data bus. For

60x single beat transfers, assertion of this pin indicates the termination of the transfer. For 60x

burst transfers TA is asserted four times to indicate the transfer of four data beats with the last

assertion indicating the termination of the burst transfer.

TEA

Transfer error acknowledge—(Input/output) Assertion of this pin indicates a bus error. 60x

masters within the MPC8280 monitor the state of this pin. MPC8280’s internal bus monitor may

assert this pin in case it identified a 60x bus transfer that is hung.

GBL

IRQ1

Global—(Input/output) When a 60x master within the chip initiates a bus transaction it drives this

pin. When an external 60x master initiates a bus transaction it should drive this pin. Assertion of

this pin indicates that the transfer is global and it should be snooped by caches in the system. The

MPC8280’s data cache monitors the state of this pin.

Interrupt request 1—This input is one of the eight external lines that can request (by means of the

internal interrupt controller) a service routine from the core.

BADDR29

IRQ2

Cache inhibit—Output pin. Used for L2 cache control. For each MPC8280 60x transaction

initiated in the core, the state of this pin indicates if this transaction should be cached or not.

Assertion of the CI pin indicates that the transaction should not be cached.

Burst address 29—There are five burst address output pins. These pins are outputs of the 60x

memory controller. These pins are used in external master configuration and are connected

directly to memory devices controlled by MPC8280’s memory controller. For information on the

use of this signal, see Section 11.2.14, “BADDR[27:31] Signal Connections.”

Interrupt request 2—This input is one of the eight external lines that can request (by means of the

internal interrupt controller) a service routine from the core.

BADDR30

IRQ3

Write through—Output used for L2 cache control. For each core-initiated MPC8280 60x

transaction, the state of this pin indicates if the transaction should be cached using write-through

or copy-back mode. Assertion of WT indicates that the transaction should be cached using the

write-through mode.

Burst address 30—There are five burst address output pins. These pins are outputs of the 60x

memory controller. These pins are used in external master configuration and are connected

directly to memory devices controlled by MPC8280’s memory controller. For information on the

use of this signal, see Section 11.2.14, “BADDR[27:31] Signal Connections.”

Interrupt request 3—This input is one of the eight external lines that can request (by means of the

internal interrupt controller) a service routine from the core.

Table 6-1. External Signals (continued)

Signal

Description

MPC8280 датащи(PDF) 248 Page - Freescale Semiconductor, Inc

MPC8280 датащи(HTML) 248 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL