PM5366 datasheet(20/267 Pages) PMC

20 / 267 page

PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

meets the ANSI T1M1.3 Section 7.1.2.4 requirement that AIS be detected in less

than 100 ms and is intended for non-BOC (Bell Operating Company)

applications.

• Extracts valid X-bits and indicates far end receive failure (FERF). The far end

receive failure status only changes if the two X-bits are the same. The status is

buffered for two M-frames, ensuring a better than 99.99% chance of freezing the

correct status for the duration of the out of frame occurrence.

• Accumulates up to 65,535 line code violation (LCV) events per second, 65,535

P-bit parity error events per second, 1023 F-bit or M-bit (framing bit) events per

second, 65,535 excessive zero (EXZ) events per second, and when enabled for

C-bit parity mode operation, up to 16,383 C-bit parity error events per second,

and 16,383 far end block error (FEBE) events per second (note that, over a one

second interval, only 9399 P-bit errors, C-bit parity errors, or FEBE events can

occur).

• Detects and validates bit-oriented codes in the C-bit parity far end alarm and

control channel.

• Terminates the C-bit parity path maintenance data link with an integral HDLC

receiver having a 128-byte deep FIFO buffer with programmable interrupt

threshold. Supports polled or interrupt-driven operation. Selectable none, one or

two address match detection on first byte of received packet.

• Programmable pseudo-random test-sequence detection–(up to 232 -1 bit length

patterns conforming to ITU-T O.151 standards) and analysis features.

Each one of three DS3 Transmit Sections:

• Provides the overhead bit insertion for a DS3 stream.

• Provides a bit serial clock and data interface, and allows the M-frame boundary

and/or the overhead bit positions to be located via an external interface

• Provides B3ZS encoding.

• Generates an B3ZS encoded 100… repeating pattern to aid in pulse mask

testing.

• Inserts far end receive failure (FERF), the DS3 alarm indication signal (AIS) and

the idle signal when enabled by internal register bits.

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