PM5366 datasheet(91/267 Pages) PMC

91 / 267 page

PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

9.8 T1/E1 Pseudo Random Binary Sequence Generation and Detection (PRBS)

The Pseudo Random Binary Sequence Generator/Detector (PRBS) is a software

selectable PRBS generator and checker for 2

7-1, 211-1, 215-1 or 220-1 PRBS

polynomials for use in the unframed T1 and E1 links. PRBS patterns may be

generated and monitored in both the transmit or receive directions for all T1 and

E1 links simultaneously. The generator is capable of inserting single bit errors

under microprocessor control.

The detector auto-synchronizes to the expected PRBS pattern and accumulates

the total number of bit errors in a 16-bit counter. The error count accumulates

over the interval defined by writes to the Global PMON Update register. When a

transfer is triggered, the holding register is updated, and the counter reset to

begin accumulating for the next interval. The counter is reset in such a way that

no events are missed. The data is then available until the next transfer.

9.9 DS3 Framer (DS3-FRMR)

Three instances of the DS3 Framer are independently programmed. From each

the framed data is presented on RDATO[x], mapped into the SBI bus or may be

demultiplexed to 28 DS1s or 21 E1s (ITU-T Rec. G.747).

The DS3 Framer (DS3-FRMR) Block integrates circuitry required for decoding a

B3ZS-encoded signal and framing to the resulting DS3 bit stream. The

DS3-FRMR is directly compatible with the M23 and C-bit parity DS3 applications.

The DS3-FRMR decodes a B3ZS-encoded signal and provides indications of line

code violations. The B3ZS decoding algorithm and the LCV definition can be

independently chosen through software. A loss of signal (LOS) defect is also

detected for B3ZS encoded streams. LOS is declared when inputs RPOS and

RNEG contain zeros for 175 consecutive RCLK cycles. LOS is removed when

the ones density on RPOS and/or RNEG is greater than 33% for 175 ±1 RCLK

cycles.

The framing algorithm examines five F-bit candidates simultaneously. When at

least one discrepancy has occurred in each candidate, the algorithm examines

the next set of five candidates. When a single F-bit candidate remains in a set,

the first bit in the supposed M-subframe is examined for the M-frame alignment

signal (i.e., the M-bits, M1, M2, and M3 are following the 010 pattern). Framing

is declared, and out-of-frame is removed, if the M-bits are correct for three

consecutive M-frames while no discrepancies have occurred in the F-bits.

During the examination of the M-bits, the X-bits and P-bits are ignored. The

algorithm gives a maximum average reframe time of 1.5 ms.

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