PM5366 datasheet(49/267 Pages) PMC

49 / 267 page

PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

Pin Name

Type

No.

Function

XCLK_T1

Input

T1 Crystal Clock Input (XCLK_T1). This input clocks

the digital phase locked loop that performs jitter

attenuation on the T1 recovered clocks which drive the

RECVCLK1/2/3 outputs. XCLK_T1 is nominally a

37.056 MHz ± 32ppm, 50% duty cycle clock.

This input may be tied to ground in applications that do

not use the RECVCLK1/2/3 outputs as 1.544 MHz

clocks.

XCLK_E1

Input

E1 Crystal Clock Input (XCLK_E1). This input clocks

the digital phase locked loop that performs jitter

attenuation on the E1 recovered clocks which drive the

RECVCLK1/2/3 outputs. XCLK_E1 is nominally a

49.152 MHz ± 32ppm, 50% duty cycle clock when

configured for E1 modes.

This input may be tied to ground in applications that do

not use the RECVCLK1/2/3 outputs as 2.048 MHz

clocks.

Telecom Line Side Interface

LREFCLK

Input

Line Reference Clock (LREFCLK). This signal

provides reference timing for the SONET telecom bus

interface. On the incoming byte interface of the

telecom bus, LDC1J1V1, LDDATA[7:0], LDDP, LDPL,

LDTPL, LDV5, LDAIS and LAC1 are sampled of the

rising edge or LREFCLK. In the outgoing byte

interface, LADATA[7:0], LADP, LAPL, LAC1J1V1 and

LAOE/LATPL are updated on the rising edge of

LREFCLK.

This clock may be held low if the Telecom Bus

interface is unused.

This clock is nominally a 19.44 MHz +/-50ppm or

77.76 MHz +/-50ppm clock with a 50% duty cycle. This

clock must be phase locked to SREFCLK and can be

external connected to SREFCLK.

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