PM5366 datasheet(93/267 Pages) PMC

93 / 267 page

PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

assert LOF, the counter will integrate up when the framer asserts an Out of

Frame condition and integrates down when the framer de-asserts the Out of

Frame condition. Once an LOF is asserted, the framer must not assert OOF for

the entire integration period before LOF is deasserted.

Valid X-bits are extracted by the DS3-FRMR to provide indication of far end

receive failure (FERF). A FERF defect is detected if the extracted X-bits are

equal and are logic 0 (X1=X2=0); the defect is removed if the extracted X-bits are

equal and are logic 1 (X1=X2=1). If the X-bits are not equal, the FERF status

remains in its previous state. The extracted FERF status is buffered for 2 M-

frames before being reported within the DS3 FRMR Status register. This buffer

ensures a better than 99.99% chance of freezing the FERF status on a correct

value during the occurrence of an out of frame.

When the C-bit parity application is enabled, both the far end alarm and control

(FEAC) channel and the path maintenance data link are extracted. Codes in the

FEAC channel are detected by the Bit Oriented Code Detector (RBOC). HDLC

messages in the Path Maintenance Data Link are received by the Data Link

Receiver (RDLC).

The DS3-FRMR can be enabled to automatically assert the RAI indication in the

outgoing transmit stream upon detection of any combination of LOS, OOF or

RED, or AIS. The DS3-FRMR can also be enabled to automatically insert C-bit

Parity FEBE upon detection of receive C-bit parity error.

The DS3-FRMR may be configured to generate interrupts on error events or

status changes. All sources of interrupts can be masked or acknowledged via

internal registers. Internal registers are also used to configure the DS3-FRMR.

Access to these registers is via a generic microprocessor bus.

9.10 DS3 Bit Oriented Code Detection

The presence of 63 of the possible 64 bit oriented codes transmitted in the T1

Facility Data Link channel in ESF framing format is detected, as defined in ANSI

T1.403 and in TR-TSY-000194 or in the DS3 C-bit parity far-end alarm and

control (FEAC) channel. The 64

Th code (111111) is similar to the HDLC flag

sequence and is used to indicate no valid code received.

Bit oriented codes are received on the Facility Data Link channel or FEAC

channel as a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a

trailing zero (111111110xxxxxx0). BOCs are validated when repeated at least 10

times. The receiver can be enabled to declare a received code valid if it has

been observed for 8 out of 10 times or for 4 out of 5 times, as specified by the

AVC context bit. The code is declared removed if two code sequences

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