PM5366 datasheet(16/267 Pages) PMC

16 / 267 page

PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

• Provides performance monitoring counters sufficiently large as to allow

performance monitor counter polling at a minimum rate of once per second.

Optionally, updates the performance monitoring counters and interrupts the

microprocessor once per second.

• An unframed pseudo-random sequence user selectable from 2

7 –1, 211 –1, 215 –

1 or 2

20 –1, may be detected in the T1 stream in either the ingress or egress

directions. The detector counts pattern errors using a 16-bit non-saturating PRBS

error counter.

• Line side interface is either from the DS3 interface via the M13 multiplex or from

the SONET/SDH Drop bus via the VT1.5, TU-11, VT2 or TU-12 demapper.

• Frames in the presence of and detects the “Japanese Yellow” alarm.

Each one of 63 E1 performance monitor sections:

• Provides non-intrusive performance monitoring of either ingress or egress paths,

as selected on a per-tributary basis.

• Frames to ITU-T G.704 basic and CRC-4 multiframe formatted E1 signals. The

framing procedures are consistent ITU-T G.706 specifications.

• Non-intrusive performance monitoring provided by the TEMAP-84 also

provides an HDLC interface with 128 bytes of buffering for terminating the

facility data link in either the ingress or egress paths, as selected on a per-

tributary basis.

• Provides performance monitoring counters sufficiently large as to allow

performance monitor counter polling at a minimum rate of once per second.

Optionally, updates the performance monitoring counters and interrupts the

microprocessor once per second.

• An unframed pseudo-random sequence user selectable from 2

7 –1, 211 –1, 215 –

1 or 2

20 –1, may be detected in the E1 stream in either the ingress or egress

directions. The detector counts pattern errors using a 16-bit non-saturating PRBS

error counter.

Each one of 84 transmit tributaries:

• May be timed to its associated receive clock (loop timing) or may derive its timing

from a common egress clock or a common transmit clock; the transmit line clock

may be synthesized from an N*8 kHz reference.

• Provides a digital phase locked loop for generation of a low jitter transmit clock.

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