PM5366 datasheet(98/267 Pages) PMC

98 / 267 page

PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

Interrupts can also be generated if the FIFO underflows while transmitting a

packet, when the FIFO falls below a lower threshold, when the FIFO is full, or if

the FIFO is overrun.

If there are more than five consecutive ones in the raw transmit data or in the

CRC data, a zero is stuffed into the serial data output. This prevents the

unintentional transmission of flag or abort sequences.

Abort characters can be continuously transmitted at any time by setting the ABT

bit. During packet transmission, an underrun situation can occur if data is not

written before the previous byte has been depleted. In this case, an abort

sequence is transmitted, and the controlling processor is notified via the UDRI

interrupt.

9.15 DS3 Pseudo Random Pattern Generation and Detection (PRGD)

The Pseudo Random Pattern Generator/Detector (PRGD) block is a software

programmable test pattern generator, receiver, and analyzer for the DS3

payload. Patterns may be generated in the transmit direction, and detected in

the receive direction. Two types of ITU-T O.151 compliant test patterns are

provided : pseudo-random and repetitive.

The PRGD can be programmed to generate any pseudo-random pattern with

length up to 232-1 bits or any user programmable bit pattern from 1 to 32 bits in

length. In addition, the PRGD can insert single bit errors or a bit error rate

between 10-1 to 10-7.

The PRGD can be programmed to check for the generated pseudo random

pattern. The PRGD can perform an auto synchronization to the expected pattern

and accumulates the total number of bits received and the total number of bit

errors in two 32-bit counters. The counters accumulate either over intervals

defined by writes to the Pattern Detector registers or upon writes to the Global

PMON Update Register. When a transfer is triggered, the holding registers are

updated, and the counters reset to begin accumulating for the next interval. The

counters are reset in such a way that no events are missed. The data is then

available in the holding registers until the next transfer.

9.16 M23 Multiplexer (MX23)

The M23 Multiplexer (MX23) integrates circuitry required to asynchronously

multiplex and demultiplex seven DS2 streams into, and out of, an M23 or C-bit

Parity formatted DS3 serial stream.

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