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PM5366 датащи(PDF) 95 Page - PMC-Sierra, Inc |
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PM5366 датащи(HTML) 95 Page - PMC-Sierra, Inc |
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95 / 267 page ![]() PRELIMINARY PM5366 TEMAP-84 DATASHEET PMC-2010672 ISSUE 1 HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER PROPRIETARY AND CONFIDENTIAL 83 • path parity error (CPERR) events • far end block error (FEBE) events • excess zeros (EXZS) • framing bit error (FERR) events Due to the off-line nature of the DS3 and E3 Framers, PMON continues to accumulate performance metrics even while the framer has declared OOF. When an accumulation interval is signaled by a write to the PMON register address space or to the Global PMON Update register, the PMON transfers the current counter values into microprocessor accessible holding registers and resets the counters to begin accumulating error events for the next interval. The counters are reset in such a manner that error events occurring during the reset period are not missed. When counter data is transferred into the holding registers, an interrupt is generated, providing the interrupt is enabled. If the holding registers have not been read since the last interrupt, an overrun status bit is set. In addition, a register is provided to indicate changes in the PMON counters since the last accumulation interval. Whenever counter data is transferred into the holding registers, an interrupt is generated, providing the interrupt is enabled. If the holding registers have not been read since the last interrupt, an overrun status bit is set. 9.13 DS3 Transmitter (DS3-TRAN) Three DS3 transmitters are instantiated. Each may be programmed to provide framing for unchannelized data from TDATI[x] or the SBI bus, or framing for multiplexed T1s or E1s (ITU-T Rec. G.747). The DS3 Transmitter (DS3-TRAN) Block integrates circuitry required to insert the overhead bits into a DS3 bit stream and produce a B3ZS-encoded signal. The T3-TRAN is directly compatible with the M23 and C-bit parity DS3 formats. Status signals such as far end receive failure (FERF), the alarm indication signal, and the idle signal can be inserted when their transmission is enabled by internal register bits. FERF can also be automatically inserted on detection of any combination of LOS, OOF or RED, or AIS by the DS3-FRMR. |
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