PM5366 datasheet(37/267 Pages) PMC

37 / 267 page

PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

parity errors, and far end block errors are accumulated. Error accumulation

continues even while the off-line framers are indicating OOF. The counters are

intended to be polled once per second, and are sized so as not to saturate at a

10-3 bit error rate. Transfer of count values to holding registers is initiated through

the microprocessor interface.

In the DS3 transmit direction, the TEMAP-84 inserts DS3 framing, X and P bits.

When enabled for C-bit parity operation, bit-oriented code transmitters and

HDLC transmitters are provided for insertion of the FEAC channels and the Path

Maintenance Data Links into the appropriate overhead bits. Alarm Indication

Signals, Far End Receive Failure and idle signal can be inserted using either

internal registers or can be configured for automatic insertion upon received

errors. When M23 operation is selected, the C-bit Parity ID bit (the first C-bit of

the first M sub-frame) is forced to toggle so that downstream equipment will not

confuse an M23-formatted stream with stuck-at-1 C-bits for C-bit Parity

application. Transmit timing is from an external reference or from the receive

direction clock.

The TEMAP-84 also supports diagnostic options which allow it to insert, when

appropriate for the transmit framing format, parity or path parity errors, F-bit

framing errors, M-bit framing errors, invalid X or P-bits, line code violations,

all-zeros, AIS, Remote Alarm Indications, and Remote End Alarms. A Pseudo

Random Binary Sequence (PRBS) can be inserted into a DS3 payload and

checked in the receive DS3 payload for bit errors. A fixed 100100… pattern is

available for insertion directly into the B3ZS encoder for proper pulse mask

shape verification.

The TEMAP-84 may be used as an E3 framer for the transport of framed but

unchannelized E3 data streams complying to the ITU-T Recommendations

G.751 or G.832. The line interface may be configured as either unipolar or

HDB3-encoded.

When configured in DS3 multiplexer mode, seven 6312 kbit/s data streams are

demultiplexed and multiplexed into and out of each DS3 signal. Bit stuffing and

rate adaptation is performed. The C-bits are set appropriately, with the option of

inserting DS2 loopback requests. Interrupts can be generated upon detection of

loopback requests in the received DS3. AIS may be inserted in the any of the

6312 kbit/s tributaries in both the multiplex and demultiplex directions. C-bit

parity is supported by sourcing a 6.3062723 MHz clock, which corresponds to a

stuffing ratio of 100%.

Framing to the demultiplexed 6312 kbit/s data streams supports DS2 (ANSI

TI.107) frame formats. The maximum average reframe time is 7ms for DS2. Far

end receive failure is detected and M-bit and F-bit errors are accumulated. The

DS2 framer is an off-line framer, indicating both OOF and COFA events. Error

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