PM5366 datasheet(59/267 Pages) PMC

59 / 267 page

PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

Pin Name

Type

No.

Function

S77

Input

D10 The SBI 77.76 MHz select input determines the

expected frequency of SREFCLK. If S77 is low,

SREFCLK is expected to be 19.44 MHz. If S77 is

high, SREFCLK is expected to be 77.76 MHz and data

is driven and sampled every fourth cycle.

This signal is a don't care when the SYSOPT register

bits are binary 01 (H-MVIP interface). In this mode,

SREFCLK is required to be 19.44 MHz.

S77 must be held static.

SDC1FP

I/O

SBI Drop C1 Frame Pulse (SDC1FP). The SDC1FP

C1 frame pulse synchronizes devices interfacing to the

Insert SBI bus. The frame pulse indicates SBI bus

multiframe alignment which occurs every 500

µS,

therefore this signal is pulsed every 9720 SREFCLK

cycles (38880 cycles if S77 is high). This signal does

not need to occur every SBI multiframe and is also

used to indicate T1 and E1 multiframe alignment in

synchronous SBI mode by pulsing at multiples of every

12 SBI multiframes (48 T1/E1 frames). In synchronous

locked mode, as selected by the SYNCSBI context bit

programmed through the RX-SBI-ELST Indirect

Channel Data register, SDC1FP pulses every 116640

SREFCLK cycles (466560 cycles if S77 is high). If the

SYNCSBI bit is logic 1 for at least one tributary,

SDC1FP must indicate T1 and E1 multiframe

alignment.

The TEMAP-84 can be configured to generate this

frame pulse. Only one device on the SBI bus should

generate this signal. By default this signal is not

enabled to generate the frame pulse.

If a SDC1FP pulse is received at an unexpected cycle,

the Drop bus with become high-impedence until two

consecutive valid SDC1FP pulses occur.

The system frame pulse is a single SREFCLK cycle

long and is updated on the rising edge of SREFCLK.

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