M25PX32-VMP6F datasheet(49/63 Pages) STMICROELECTRONICS

49 / 63 page

M25PX32

Power-up and Power-down

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Power-up and Power-down

At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must

follow the voltage applied on VCC) until VCC reaches the correct value:

●

VCC(min) at Power-up, and then for a further delay of tVSL

●

VSS at Power-down

A safe configuration is provided in Section 3: SPI modes.

To avoid data corruption and inadvertent write operations during Power-up, a Power On

Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less

than the Power On Reset (POR) threshold voltage, VWI – all operations are disabled, and

the device does not respond to any instruction.

Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Dual Input Fast

Program (DIFP), Program OTP (POTP), Subsector Erase (SSE), Sector Erase (SE), Bulk

Erase (BE), Write Status Register (WRSR) and Write to Lock Register (WRLR) instructions

until a time delay of tPUW has elapsed after the moment that VCC rises above the VWI

threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC

is still below VCC(min). No Write Status Register, Program or Erase instructions should be

sent until the later of:

●

tPUW after VCC has passed the VWI threshold

●

tVSL after VCC has passed the VCC(min) level

These values are specified in Table 11.

If the time, tVSL, has elapsed, after VCC rises above VCC(min), the device can be selected for

READ instructions even if the tPUW delay has not yet fully elapsed.

After Power-up, the device is in the following state:

●

The device is in the Standby Power mode (not the Deep Power-down mode).

●

The Write Enable Latch (WEL) bit is reset.

●

The Write In Progress (WIP) bit is reset.

●

The Lock Registers are configured as: (Write Lock bit, Lock Down bit) = (0,0)

Normal precautions must be taken for supply line decoupling, to stabilize the VCC supply.

Each device in a system should have the VCC line decoupled by a suitable capacitor close to

the package pins (generally, this capacitor is of the order of 100 nF).

At Power-down, when VCC drops from the operating voltage, to below the Power On Reset

(POR) threshold voltage, VWI, all operations are disabled and the device does not respond

to any instruction. (The designer needs to be aware that if Power-down occurs while a Write,

Program or Erase cycle is in progress, some data corruption may result.)

●

VPPH must be applied only when VCC is stable and in the VCCmin to VCCmax voltage

range.

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