M25PX32-VMP6F datasheet(23/63 Pages) STMICROELECTRONICS

23 / 63 page

M25PX32

Instructions

23/63

Instructions

All instructions, addresses and data are shifted in and out of the device, most significant bit

first.

Serial Data input(s) DQ0 (DQ1) is (are) sampled on the first rising edge of Serial Clock (C)

after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to

the device, most significant bit first, on Serial Data input(s) DQ0 (DQ1), each bit being

latched on the rising edges of Serial Clock (C).

The instruction set is listed in Table 5.

Every instruction sequence starts with a one-byte instruction code. Depending on the

instruction, this might be followed by address bytes, or by data bytes, or by both or none.

In the case of a Read Data Bytes (READ), Read Data Bytes at higher speed (Fast_Read),

Dual Output Fast Read (DOFR), Read OTP (ROTP), Read Lock Registers (RDLR), Read

Status Register (RDSR), Read Identification (RDID) or Release from Deep Power-down

(RDP) instruction, the shifted-in instruction sequence is followed by a data-out sequence.

Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted

out.

In the case of a Page Program (PP), Program OTP (POTP), Dual Input Fast Program

(DIFP), Subsector Erase (SSE), Sector Erase (SE), Bulk Erase (BE), Write Status Register

(WRSR), Write to Lock Register (WRLR), Write Enable (WREN), Write Disable (WRDI) or

Deep Power-down (DP) instruction, Chip Select (S) must be driven High exactly at a byte

boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S)

must driven High when the number of clock pulses after Chip Select (S) being driven Low is

an exact multiple of eight.

All attempts to access the memory array during a Write Status Register cycle, Program

cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program

cycle or Erase cycle continues unaffected.

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