M25PX32-VMP6F datasheet(29/63 Pages) STMICROELECTRONICS

номер детали	M25PX32-VMP6F

подробное описание детали	32-Mbit, dual I/O, 4-Kbyte subsector erase, serial Flash memory with 75 MHz SPI bus interface

PDF	63 Pages

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производитель	STMICROELECTRONICS [STMicroelectronics]

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M25PX32

Instructions

29/63

6.4.4

TB bit

The Top/Bottom (TB) bit is non-volatile. It can be set and reset with the Write Status

issued. The Top/Bottom (TB) bit is used in conjunction with the Block Protect (BP0, BP1,

BP2) bits to determine if the protected area defined by the Block Protect bits starts from the

top or the bottom of the memory array:

●

When TB is reset to ‘0’ (default value), the area protected by the Block Protect bits

starts from the top of the memory array (see Table 3: Protected area sizes)

●

When TB is set to ‘1’, the area protected by the Block Protect bits starts from the

bottom of the memory array (see Table 3: Protected area sizes)

The TB bit cannot be written when the SRWD bit is set to ‘1’ and the W pin is driven Low.

6.4.5

SRWD bit

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write

Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and the Write Protect

(W/VPP) signal allow the device to be put in the hardware protected mode (when the Status

this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become

read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for

execution.

Figure 11.

Read Status Register (RDSR) instruction sequence and data-out

sequence

DQ0

3456789 10 11 12 13 14 15

Instruction

AI13734

DQ1

6543210

Status Register Out

High Impedance

MSB

6543210

Status Register Out

MSB

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