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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M25PX32-VMP6F датащи(PDF) 15 Page - STMicroelectronics |
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M25PX32-VMP6F датащи(HTML) 15 Page - STMicroelectronics |
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15 / 63 page  M25PX32 Operating features 15/63 4.8 Protection modes There are protocol-related and specific hardware and software protection modes. They are described below. 4.8.1 Protocol-related protections The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25PX32 features the following data protection mechanisms: ● Power On Reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification ● Program, Erase and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution ● All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: –Power-up – Write Disable (WRDI) instruction completion – Write Status Register (WRSR) instruction completion – Write to Lock Register (WRLR) instruction completion – Program OTP (POTP) instruction completion – Page Program (PP) instruction completion – Dual Input Fast Program (DIFP) instruction completion – Subsector Erase (SSE) instruction completion – Sector Erase (SE) instruction completion – Bulk Erase (BE) instruction completion ● In addition to the low power consumption feature, the Deep Power-down mode offers extra software protection, as all Write, Program and Erase instructions are ignored. |
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