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M25PX32-VMP6F датащи(PDF) 17 Page - STMicroelectronics |
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M25PX32-VMP6F датащи(HTML) 17 Page - STMicroelectronics |
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17 / 63 page ![]() M25PX32 Operating features 17/63 As a second level of protection, the Write Protect signal (applied on the W/VPP pin) can freeze the Status Register in a read-only mode. In this mode, the Block Protect bits (BP2, BP1, BP0) and the Status Register Write Disable bit (SRWD) are protected. For more details, see Section 6.5: Write Status Register (WRSR). Table 3. Protected area sizes Status Register contents Memory content TB bit BP bit 2 BP bit 1 BP bit 0 Protected area Unprotected area 0 0 0 0 none All sectors(1) (64 sectors: 0 to 63) 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0. 0 0 0 1 Upper 64th (Sector 63) Lower 63/64ths (63 sectors: 0 to 62) 0 0 1 0 Upper 32nd (two sectors: 62 and 63) Lower 31/32nds (62 sectors: 0 to 61) 0 0 1 1 Upper sixteenth (four sectors: 60 to 63) Lower 15/16ths (60 sectors: 0 to 59) 0 1 0 0 Upper eighth (eight sectors: 56 to 63) Lower seven-eighths (56 sectors: 0 to 55) 0 1 0 1 Upper quarter (sixteen sectors: 48 to 63) Lower three-quarters (48 sectors: 0 to 47) 0 1 1 0 Upper half (thirty-two sectors: 32 to 63) Lower half (32 sectors: 0 to 31) 0 1 1 1 All sectors (64 sectors: 0 to 63) none 1 0 0 0 none All sectors(1) (64 sectors: 0 to 63) 1 0 0 1 Lower 64th (sector 0) Upper 63/64ths (63 sectors: 1 to 63) 1 0 1 0 Lower 32nd (two sectors: 0 and 1) Upper 31/32ths (62 sectors: 2 to 63) 1 0 1 1 Lower 16th (four sectors: 0 to 3) Upper 15/16ths (60 sectors: 4 to 63) 1 1 0 0 Lower 8th (eight sectors: 0 to 7) Upper 7/8ths (56 sectors: 8 to 63) 1 1 0 1 Lower 4th (sixteen sectors: 0 to 15) Upper 3/4ths (48 sectors: 16 to 63) 1 110 Lower half (thirty-two sectors: 0 to 31) Upper half (32 sectors: 32 to 63) 1 1 1 1 All sectors (64 sectors: 0 to 63) none |
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