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M25PX32-VMP6F датащи(PDF) 36 Page - STMicroelectronics

номер детали M25PX32-VMP6F
подробное описание детали  32-Mbit, dual I/O, 4-Kbyte subsector erase, serial Flash memory with 75 MHz SPI bus interface
PDF  63 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M25PX32-VMP6F датащи(HTML) 36 Page - STMicroelectronics

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Instructions
M25PX32
36/63
6.10
Read OTP (ROTP)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
OTP (ROTP) instruction is followed by a 3-byte address (A23- A0) and a dummy byte. Each
bit is latched in on the rising edge of Serial Clock (C).
Then the memory contents at that address are shifted out on Serial Data output (DQ1).
Each bit is shifted out at the maximum frequency, fCmax, on the falling edge of Serial Clock
(C). The instruction sequence is shown in Figure 17.
The address is automatically incremented to the next higher address after each byte of data
is shifted out.
There is no rollover mechanism with the Read OTP (ROTP) instruction. This means that the
Read OTP (ROTP) instruction must be sent with a maximum of 65 bytes to read, since once
the 65th byte has been read, the same (65th) byte keeps being read on the DQ1 pin.
The Read OTP (ROTP) instruction is terminated by driving Chip Select (S) High. Chip Select
(S) can be driven High at any time during data output. Any Read OTP (ROTP) instruction
issued while an Erase, Program or Write cycle is in progress, is rejected without having any
effect on the cycle that is in progress.
Figure 17.
Read OTP (ROTP) instruction and data-out sequence
1.
A23 to A7 are Don't care.
2.
1
≤ n ≤ 65.
C
DQ0
AI13573
S
DQ1
23
2
1
3456789 10
28 29 30 31
22 21
3210
High Impedance
Instruction
24-bit address
0
C
DQ0
S
DQ1
32 33 34
36 37 38 39 40 41 42 43 44 45 46
765432
0
1
DATA OUT 1
Dummy byte
MSB
7
6543210
DATA OUT n
MSB
MSB
7
47
765432
0
1
35



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