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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MFS5600AMBAFES датащи(PDF) 117 Page - NXP Semiconductors |
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MFS5600AMBAFES датащи(HTML) 117 Page - NXP Semiconductors |
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117 / 118 page  NXP Semiconductors FS5600 Automotive buck regulator and controller with voltage monitors and watchdog timer Contents 1 General description .........................................1 2 Features and benefits ..................................... 2 2.1 Overview ............................................................2 3 Applications ..................................................... 3 4 Ordering information .......................................4 5 FS5600 internal block diagram .......................6 6 Regulator input configurations ...................... 7 7 Pinout and pin description ............................. 8 8 ESD ratings .................................................... 11 9 Thermal characteristics ................................ 12 10 Device level electrical parameters ............... 13 11 SW1: 36 V integrated FET DC-DC converter .........................................................14 11.1 SW1 electrical specifications ........................... 14 11.2 SW1 external component selection ................. 15 11.3 SW1 operation .................................................15 11.3.1 Output voltage selection .................................. 15 11.3.2 PFM and pulse skipping operation .................. 19 11.3.3 PFM operation ................................................. 19 11.3.4 Soft-start .......................................................... 20 11.3.5 Current limit protection .................................... 20 11.3.6 Compensation selection .................................. 20 11.3.7 SW1 fault monitoring ....................................... 21 12 SW2: 36 V DC-DC controller with external FETs ................................................. 22 12.1 SW2 electrical characteristics ..........................22 12.2 SW2 operation .................................................23 12.2.1 SW2 external component selection ................. 23 12.2.1.1 Compensation network .................................... 24 12.2.1.2 Inductor current sense selection ......................24 12.2.2 Output voltage selection .................................. 26 12.2.3 Pulse skipping operation ................................. 28 12.2.4 PFM operation ................................................. 28 12.2.5 Soft-start .......................................................... 29 12.2.6 Current limit protection .................................... 29 12.2.7 Slope compensation ........................................ 29 12.2.8 SW2 fault monitoring ....................................... 31 13 BIAS_IN input .................................................32 14 FS5600 clock management ...........................33 14.1 FS5600 clock electrical characteristics ............ 33 14.2 High frequency oscillator ................................. 34 14.3 Spread spectrum ............................................. 35 14.4 SW1 and SW2 switching frequency selection ...........................................................35 14.5 External clock synchronization ........................ 35 14.6 SYNCOUT function settings ............................ 36 15 I/O pins in FS5600 ......................................... 37 15.1 I/O pins electrical specifications .......................37 15.2 EN1 and EN2 .................................................. 37 15.2.1 Programming turn-off delay ............................. 38 15.3 PGOOD1 and PGOOD2 ..................................38 15.4 GPIO1/2/3 ........................................................38 15.5 MODE pin ........................................................39 15.6 I2C communication ..........................................39 16 Thermal protection ........................................ 41 17 Functional safety features in FS5600 ...........42 17.1 GPIO1/2/3 feature selection ............................ 42 17.2 OV/UV monitors ...............................................43 17.2.1 VMON1-4 electrical specifications ................... 43 17.3 Watchdog .........................................................45 17.3.1 Simple watchdog ............................................. 47 17.3.2 Challenger watchdog .......................................47 17.3.3 Watchdog error counter and error impact ........ 47 17.3.4 Watchdog refresh counter ............................... 49 17.4 FCCU monitoring .............................................50 17.4.1 BI_STABLE protocol with FCCU1 and FCCU2 .............................................................50 17.4.2 Single/independent FCCU monitoring ............. 51 17.4.3 FCCU status reporting via interrupt register .....51 17.5 External signal monitoring using ERRMON ..... 51 17.6 PGOOD1/2 programmable reactions for ASIL B and Enhanced ASIL B versions ...........52 17.6.1 Watchdog impact on PGOOD1/2 .....................53 17.7 FS0B pin ..........................................................54 17.7.1 FS0B pin electrical specifications .................... 54 17.8 PGOOD1, PGOOD2, FS0B stuck at fault check ................................................................54 17.9 I2C robustness ................................................ 54 17.9.1 I2C CRC verification ........................................54 17.9.2 NOT logic registers ..........................................55 17.10 I2C write protection ......................................... 55 17.11 Fault error counter ...........................................56 17.12 Latent failure detection .................................... 57 17.12.1 Analog built-in self-test (ABIST) .......................57 17.12.2 On-demand ABIST .......................................... 58 17.12.3 Logical built-In self-test (LBIST) .......................58 17.12.4 VCC and VDIG monitoring .............................. 59 17.13 FS5600 operation states and state machine ....59 17.13.1 Shutdown mode ...............................................60 17.13.2 Built-in self-test (BIST) .....................................60 17.13.3 Power-up ..........................................................60 17.13.4 Power-up in Debug mode ................................61 17.13.5 INIT_RUN ........................................................ 61 17.13.6 Normal state .................................................... 61 17.13.7 Deep fail-safe state ......................................... 62 17.13.8 Power-down .....................................................62 17.13.9 Low-power operation ....................................... 62 17.13.9.1 Ultra low-power operation ................................62 17.13.10 State transition table ........................................62 18 I2C register map ............................................ 66 18.1 Register descriptions ....................................... 74 18.1.1 SW1CTRL register ...........................................74 18.1.2 NOT_SW1CTRL register ................................. 74 18.1.3 SW2CTRL register ...........................................75 18.1.4 NOT_SW2CTRL register ................................. 75 18.1.5 GPIO_CTRL register ....................................... 75 18.1.6 NOT_GPIO_CTRL register ..............................76 18.1.7 CLOCK_CTRL register .................................... 77 18.1.8 NOT_CLOCK_CTRL register ...........................77 18.1.9 WATCHDOG_CTRL1 register ..........................77 18.1.10 NOT_WATCHDOG_CTRL1 register ................ 79 18.1.11 WATCHDOG_CTRL2 register ..........................79 FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 29 April 2024 117 / 118 |
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