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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MFS5600AMBAFES датащи(PDF) 50 Page - NXP Semiconductors |
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MFS5600AMBAFES датащи(HTML) 50 Page - NXP Semiconductors |
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50 / 118 page  NXP Semiconductors FS5600 Automotive buck regulator and controller with voltage monitors and watchdog timer WD refresh NOT OK / WD OFF WD refresh OK WD refresh NOT OK / WD OFF WD refresh OK WD refresh NOT OK / WD OFF WD refresh OK WD refresh NOT OK / WD OFF WD refresh OK WD refresh OK WD refresh OK WD refresh OK WD refresh OK WD refresh OK 0 1 2 3 4 5 6 WD refresh OK aaa-031019 WD refresh NOT OK / WD OFF WD refresh NOT OK / WD_OFF WD refresh NOT OK / WD_OFF WD refresh NOT OK / WD_OFF WD refresh OK WD refresh OK WD refresh OK WD refresh OK 0 1 2 3 4 WD refresh NOT OK / WD OFF WD refresh OK WD refresh OK 0 1 2 WD refresh NOT OK / WD OFF WD refresh OK 0 1 WD refresh NOT OK / WD OFF WD_RFR_LIMIT = 00 WD_RFR_LIMIT = 01 WD_RFR_LIMIT = 10 WD_RFR_LIMIT = 11 Figure 15. Watchdog refresh counter configurations See Section 17.11 on Fault Error Counter for impact of watchdog refresh on the fault error counter value. 17.4 FCCU monitoring GPIO2 and GPIO3 pins can be configured as FCCU1 and FCCU2 respectively via OTP. OTP_GPIO2_CFG[1:0] = 0b01 configures GPIO2 as FCCU1. OTP_GPIO3_CFG[1:0] = 0b01 configures GPIO3 as FCCU2. The FCCU1/2 input pins are in charge of monitoring HW failure outputs from an NXP MCU, or any other error output coming from other MCUs. FCCU can be configured by pair, or single independent inputs. Monitoring of the FCCU pins is active when the state machine is in the NORMAL STATE. See Section 17.13 on thestate machine for reactions based on FCCU monitoring. 17.4.1 BI_STABLE protocol with FCCU1 and FCCU2 When both GPIO2 and GPIO3 are configured as FCCU1 and FCCU2 respectively and FCCU12_BISTABLE = 1, a bi-stable protocol used in the NXP MCUs for FCCU is enabled. The bi-stable protocol representation is shown in Figure 16. aaa-037159 Error Condition Normal Condition Don't Care FCCU1 FCCU2 INIT_RUN NORMAL FCCU1/2 Bi-Stable Protocol example for FCCU12_FLT_POL = 0 INIT_RUN Figure 16. FCCU 1/2 bi-stable protocol example The polarity of the fault signals is configurable using FCCU12_FLT_POL register: FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 29 April 2024 50 / 118 |
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