MFS5600AMBAFES datasheet(60/118 Pages) NXP

60 / 118 page

NXP Semiconductors

FS5600

Automotive buck regulator and controller with voltage monitors and watchdog timer

aaa-037161

BOS and

Internal Core

Power Up

Any state after

Internal Core

Power Up

ABIST/LBIST

Complete/Bypassed

EN1 or EN2 = HIGH

EN1 = EN2 = LOW

Wait for valid

VDIG, VCC

BIST

(optional)

Any State after

BIST

Thermal

Shutdown

Deep Fail Safe

(FS0B = 0)

INIT_RUN

(FS0B = 0)

NORMAL

STATE

(FS0B = 1)

On Demand ABIST

(FS0B = 1 for D1-E1)

(FS0B = 0 for D2-E2)

Shutdown Mode

Power Up

ULPM Mode

System ON

Transition

System OFF

Power Down

Figure 19. FS5600 state diagram

17.13.1 Shutdown mode

This is the state of the FS5600 when a valid VIN is applied, but EN1 and EN2 pins are held low.

From one of the operation modes, (INIT_RUN/NORMAL STATE/On Demand ABIST, deep fail-safe), when EN1

and EN2 = 0, the IC enters the shut-down mode through the 'Power Down' state.

When entering the shut-down mode from INIT_RUN, NORMAL STATE or on-demand ABIST states, the FS5600

sequences the GPOs in the reverse order of the power-up at the appropriate time. See Section 17.13.8 for

details.

For example, if OTP_GPO1_DELAY is set to 1 ms, and OTP_GPO2_DELAY is set to 5 ms:

• When EN1 = EN2 = 0, GPO2 is asserted low immediately, 4 ms after which GPO1 is asserted low, 1 ms after

which SW1 and SW2 regulators are disabled.

• FS0B is asserted low immediately after NORMAL STATE is exited.

17.13.2 Built-in self-test (BIST)

Analog Built-in self-test (ABIST) and logical built-in self-test (LBIST) are executed in this state if enabled. This

state is bypassed if both are disabled.

17.13.3 Power-up

SW1, SW2, and the various GPOs in FS5600 are powered up in this state. SW1 and SW2 are enabled

after exiting BIST or thermal shutdown and if their respective ENx pin is held high. The power-up state

exits upon completion of the highest delay among OTP_GPO1_DELAY[2:0], OTP_GPO2_DELAY[2:0] and

OTP_GPO3_DELAY[2:0].

FS5600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 29 April 2024

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