MFS5600AMBAFES datasheet(57/118 Pages) NXP

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NXP Semiconductors

FS5600

Automotive buck regulator and controller with voltage monitors and watchdog timer

OTP bit

Fault counter configuration

OTP_SW1_FLT_CNT_EN = 1

enables SW1 OV and/or UV faults to increment FLT_ERR_CNT if

the SW1 OV and/or UV faults are assigned to either of the PGOODx

pins.

OTP_SW2_FLT_CNT_EN = 1

enables SW2 OV and/or UV faults to increment FLT_ERR_CNT if

the SW2 OV and/or UV faults are assigned to either of the PGOODx

pins.

OTP_VMON1_FLT_CNT_EN = 1

enables VMON1 OV and/or UV faults to increment FLT_ERR_CNT

if the VMON1 OV and/or UV faults are assigned to either of the

PGOODx pins.

OTP_VMON2_FLT_CNT_EN = 1

enables VMON2 OV and/or UV faults to increment FLT_ERR_CNT

if the VMON2 OV and/or UV faults are assigned to either of the

PGOODx pins.

OTP_VMON3_FLT_CNT_EN = 1

enables VMON3 OV and/or UV faults to increment FLT_ERR_CNT

if the VMON3 OV and/or UV faults are assigned to either of the

PGOODx pins.

OTP_VMON4_FLT_CNT_EN = 1

enables VMON4 OV and/or UV faults to increment FLT_ERR_CNT

if the VMON4 OV and/or UV faults are assigned to either of the

PGOODx pins.

OTP_ERRMON1_FLT_CNT_EN = 1[1]

increments FLT_ERR_CNT if a valid fault on the ERRMON1 pin is

detected.

OTP_ERRMON2_FLT_CNT_EN = 1[1]

increments FLT_ERR_CNT if a valid fault on the ERRMON2 pin is

detected.

OTP_FCCU_FLT_CNT_EN = 1

increments FLT_ERR_CNT if a valid fault on the FCCU1/FCCU2 pin

is detected

Table 50. Fault counter source assignment

[1]

FLT_ERR_CNT increment due to an ERRMON1/2 fault occurs only in the NORMAL STATE. If a fault occurs in the ERRMON1/2 in the INIT_RUN state,

the FLT_ERR_CNT is not incremented.

17.12 Latent failure detection

17.12.1 Analog built-in self-test (ABIST)

Analog Built In Self-test (ABIST) may be enabled via OTP by setting the OTP_ABIST_EN bit. ABIST is

bypassed if OTP_ABIST_EN = 0. If enabled, the following actions are performed.

• CRC check on mirror registers

• Checking that internal oscillators are within 15% tolerance

• Checking main band gap and monitoring band gap are within 12% of each other

• ABIST on SW1, SW2, VMON1, VMON2, VMON3, VMON4 voltage monitors.

• Check on PGOOD1, PGOOD2, and FS0B pins (check if PGOOD1, PGOOD2, and FS0B pins are low during

ABIST)

GPIO pins when used as inputs (FCCU/ERRMON) can be checked at the system level using real-time status

registers (GPIO1/2/3_RT).

Results from ABIST are stored in registers for evaluation by the processor.

The system microcontroller shall be responsible to evaluate the ABIST results and determine if the FS5600 can

proceed to the NORMAL STATE.

FS5600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 29 April 2024

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