MFS5600AMBAFES datasheet(62/118 Pages) NXP

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NXP Semiconductors

FS5600

Automotive buck regulator and controller with voltage monitors and watchdog timer

17.13.7 Deep fail-safe state

In the deep fail-safe state, the FS5600 is shut down. All the regulators are turned off and signal outputs are

asserted low. The only way to exit deep fail-safe state is through a power cycle on the VIN input, or if both EN1

and EN2 are pulled low in the application.

Deep fail-safe can be entered when the fault error counter reaches is maximum value, or when a watchdog

failure is programmed to go to deep fail-safe. OTP_DFS_EN must be set to 1 to enable transition to the deep

fail-safe state. See Section 17.13.10 for detailed conditions.

17.13.8 Power-down

The FS56 enters a graceful power-down when both EN1 and EN2 are asserted low in the application.

The power-down follows a reverse of the power-up sequence for the GPOs (each following the

OTP_GPOx_DELAY[2:0] setting) followed by SW1 and/or SW2.

If entering power-down from deep fail-safe, thermal shut-down, or power-up, the state machine immediately

enters shut-down mode after SW1, SW2, and GPIOs are asserted low (no power-down sequence).

17.13.9 Low-power operation

There are several ways to reduce the quiescent current consumption of the FS5600. These are:

• Turning off SW1 and SW2 (via I2C, or using EN1/2 pins)

• Changing SW1 and SW2 operation mode from PWM to Auto Skip or PFM mode.

The operation mode of SW1 and SW2 may be changed using I2C or by using the MODE pin.

17.13.9.1 Ultra low-power operation

When (MODE pin =1) AND (OTP_MODE_SYNCINB_SEL[1:0] = 00) AND (OTP_ULPM_EN = 1), the FS5600

achieves further reduction in quiescent current by turning off the internal 20 MHz clock. In this condition,

I2C access is not available, the watchdog timer function is not available and external voltage monitors

(VMON1-4) are disabled. PGOOD pins assigned to the external voltage monitors (VMON1-4) are asserted

low. If the respective regulator is enabled, voltage monitors for SW1 and SW2 regulators remain enabled. The

OTP_ULPM_EN bit is set to 1 in the QM version of FS5600. The user may choose its value in ASIL B and

Enhanced ASIL B versions.

17.13.10 State transition table

Transition

Description

Transition conditions

Power up to INIT_RUN

Completion of SW1 soft-start (if EN1 = high)

Completion of SW2 soft-start (if EN2 = high)

Expiration of largest delay among OTP_GPOx_DELAY[2:0] (if GPIOx pin

used as GPO AND OTP_GPOx_DELAY[2:0] NOT EQUAL to 0b000)

Note: If one regulator is disabled, its soft-start completion signal is ignored

as a condition for this state transition.

INIT_RUN to NORMAL

STATE

OTP_NORMAL STATE_EN = 1 &&

[

(PGOOD1 released high internally && OTP_PGOOD1_SAFE = 1) OR (OTP_

PGOOD1_SAFE = 0)

Table 53. State transition table

FS5600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 29 April 2024

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