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MFS5600AMBAFES датащи(PDF) 115 Page - NXP Semiconductors

номер детали MFS5600AMBAFES
подробное описание детали  Automotive buck regulator and controller with voltage monitors and watchdog timer
PDF  118 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

MFS5600AMBAFES датащи(HTML) 115 Page - NXP Semiconductors

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NXP Semiconductors
FS5600
Automotive buck regulator and controller with voltage monitors and watchdog timer
Tables
Tab. 1.
Device options ...................................................4
Tab. 2.
Ordering information ..........................................4
Tab. 3.
Pin description ...................................................9
Tab. 4.
ESD ratings .....................................................11
Tab. 5.
Temperature range ..........................................12
Tab. 6.
QFN32 thermal resistance and package
dissipation ratings ........................................... 12
Tab. 7.
Device level electrical parameters ...................13
Tab. 8.
SW1 electrical specifications ...........................14
Tab. 9.
SW1 external component selection .................15
Tab. 10. OTP_SW1_VOLT[7:0] selection ...................... 16
Tab. 11. OTP_SW1_MIN_TON[1:0] selection ............... 19
Tab. 12. SW1_MODE[1:0] selection. .............................19
Tab. 13. OTP_SW1_PFM_TON[1:0] selection .............. 19
Tab. 14. SW1 compensation selection ..........................20
Tab. 15. OTP_SW1_SLOPECOMP[1:0] Value ..............21
Tab. 16. OTP_SW1_GM_COMP[1:0] Value ..................21
Tab. 17. OTP_SW1_PWM_R_COMP[2:0] Value .......... 21
Tab. 18. SW2 electrical characteristics ......................... 22
Tab. 19. SW2 recommended external components .......23
Tab. 20. MOSFET selection .......................................... 24
Tab. 21. SW2 Compensation selection ......................... 24
Tab. 22. OTP_SW2_VOLT[5:0] Selection ..................... 26
Tab. 23. OTP_SW2_TON_MIN[1:0] Selection ...............28
Tab. 24. SW2_MODE[2:0] selection ..............................28
Tab. 25. OTP_SW2_PFM_TON[1:0] Selection ..............28
Tab. 26. OTP_SW2_SLOPECOMP[5:0] selection .........29
Tab. 27. FS5600 clock electrical characteristics ............33
Tab. 28. Internal oscillator frequency selection ............. 34
Tab. 29. SW1 and SW2 switching frequency
selection .......................................................... 35
Tab. 30. I/O pin electrical specifications ........................37
Tab. 31. PGOOD1/2, GPIO1/2/3 delay selection .......... 39
Tab. 32. I2C address selection ......................................39
Tab. 33. Thermal protection characteristics ...................41
Tab. 34. GPIO1 function selection ................................ 42
Tab. 35. GPIO2 function selection ................................ 42
Tab. 36. GPIO3 function selection ................................ 43
Tab. 37. VMON1-4 electrical specifications ...................43
Tab. 38. Watchdog window period configuration ...........46
Tab. 39. Watchdog window duty cycle configuration ..... 46
Tab. 40. Watchdog error counter ...................................48
Tab. 41. WD_FAIL_IMPACT[1:0] description .................48
Tab. 42. Watchdog refresh counter configuration ..........49
Tab. 43. FCCU1/2 status reporting error scenarios .......51
Tab. 44. ERRMON acknowledge timer selection .......... 52
Tab. 45. PGOOD1/2 programmable reactions .............. 52
Tab. 46. FS0B pin electrical specifications ....................54
Tab. 47. List of registers modifiable only during
INIT_RUN state ...............................................55
Tab. 48. INIT_RUN protected registers after first
WD_OK if watchdog enabled. ......................... 56
Tab. 49. FLT_ERR_CNT_LIMIT[1:0] description ........... 56
Tab. 50. Fault counter source assignment .................... 57
Tab. 51. ABIST flag bits ................................................ 58
Tab. 52. POR Thresholds ..............................................59
Tab. 53. State transition table ....................................... 62
Tab. 54. I2C register map ............................................. 67
Tab. 55. FS5600 register map bit-types ........................ 74
Tab. 56. SW1CTRL register description ........................74
Tab. 57. NOT_SW1CTRL register description .............. 74
Tab. 58. SW2CTRL register description ........................75
Tab. 59. NOT_SW2CTRL register description .............. 75
Tab. 60. GPIO_CTRL register description .....................75
Tab. 61. NOT_GPIO_CTRL register description ........... 76
Tab. 62. CLOCK_CTRL register description ................. 77
Tab. 63. NOT_CLOCK_CTRL register description ........77
Tab. 64. WATCHDOG_CTRL1 register description .......77
Tab. 65. NOT_WATCHDOG_CTRL1 register
description ....................................................... 79
Tab. 66. WATCHDOG_CTRL2 register description .......79
Tab. 67. NOT_WATCHDOG_CTRL2 register
description ....................................................... 80
Tab. 68. WATCHDOG_SEED register description .........80
Tab. 69. WATCHDOG_ANSWER register
description ....................................................... 80
Tab. 70. OD_ABIST_CTRL register description ............ 81
Tab. 71. NOT_OD_ABIST register description ..............81
Tab. 72. BIST_STATUS1 register description ................81
Tab. 73. BIST_STATUS2 register description ................83
Tab. 74. FAULT_CTRL register description ...................83
Tab. 75. NOT_FAULT_CTRL register description ......... 84
Tab. 76. VMON_STS register description ..................... 84
Tab. 77. VMON_RT register description ....................... 86
Tab. 78. GPIO_STS register description ....................... 87
Tab. 79. FCCU_CFG register description ..................... 88
Tab. 80. NOT_FCCU_CFG register description ............ 89
Tab. 81. STATE_CTRL register description ...................89
Tab. 82. NOT_STATE_CTRL register description ......... 90
Tab. 83. STATE register description ..............................90
Tab. 84. ID1 register description ................................... 90
Tab. 85. ........................................................................112
FS5600
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 4 — 29 April 2024
115 / 118



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