MFS5600AMBAFES datasheet(51/118 Pages) NXP

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NXP Semiconductors

FS5600

Automotive buck regulator and controller with voltage monitors and watchdog timer

• When FCCU12_FLT_POL = 0, FCCU1 = 0 or FCCU2 = 1 is a fault

• When FCCU12_FLT_POL = 1, FCCU1 = 1 or FCCU2 = 0 is a fault

The FS0B is asserted when an FCCU fault is detected and the state machine returns to INIT_RUN state.

It is possible to program the PGOOD1 and PGOOD2 pins to also toggle during an FCCU fault if they are

programmed to do so via OTP. PGOOD1/2 may be used to assert RESET of the MCU in this case. See

Section 17.6 on PGOOD for details.

17.4.2 Single/independent FCCU monitoring

When FCCU12_BISTABLE = 0, FCCU1 and FCCU2 may be used for independent signal monitoring.

Either or both FCCU pins may be used in this configuration.

For FCCU1/2 the polarity of the fault signal is configurable using FCCU1/2_FLT_POL register:

• When FCCUx_FLT_POL = 0, LOW level on FCCUx is a fault

• When FCCUx_FLT_POL = 1, HIGH-level on FCCUx is a fault

The FS0B pin is asserted when an FCCU fault is detected and the state machine returns to INIT_RUN state.

It is possible to program the PGOOD1 and PGOOD2 pins also to assert during an FCCU fault. PGOOD1/2 may

be used to assert RESET of the MCU in this case.

17.4.3 FCCU status reporting via interrupt register

The FCCU12_ERR bit is set high when an error in FCCU12 (bi-stable) is detected. FCCU1_ERR bit is set high

when an error in FCCU1 is detected. FCCU2_ERR bit is set high when an error in FCCU2 is detected. Table 43

summarizes the error scenarios for FCCU1/2.

FCCU1/2FLT_POL

FCCU1 pin

FCCU2 pin

Status

Error

No Error

Error

No Error

Error

Table 43. FCCU1/2 status reporting error scenarios

17.5 External signal monitoring using ERRMON

GPIO1 and GPIO3 may be configured as ERRMON1 and ERRMON2 by setting OTP_GPIO1_CFG[1:0] = 0b10

and OTP_GPIO3_CFG[1:0] = 0b10 respectively. When used as ERRMON1/2, GPIO1/3 may be used to monitor

an external signal on the application that is indicative of an error outside the FS56. For example, ERRMON1

could be connected to the PGOOD output of a PMIC and ERRMON2 could be connected to the PGOOD of a

secondary PMIC.

The ERRMON1/2 input is activated on entering the INIT_RUN state.

Once in the INIT_RUN state, the ERRMON1/2 pin is monitored to decide whether to the transition to the

NORMAL STATE.

FS5600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 29 April 2024

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