CLRC663 datasheet(95/177 Pages) NXP

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NXP Semiconductors

CLRC663

High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus

9.13.2 LFO_Trimm

Bit

Symbol

LFO_trimm

Access

rights

r/w

Table 173. LFO_Trimm register (address 3Ch)

Bit

Symbol

Description

7 to 0

LFO_trimm

Trimm value. Refer to Section 8.8.3.

Note: If the trimm value is increased, the frequency of the oscillator decreases.

Table 174. LFO_Trimm bits

9.13.3 PLL_Ctrl Register

The PLL_Ctrl register implements the control register for the IntegerN PLL. Two stages exist to create the

ClkOut signal from the 27.12 MHz input. In the first stage, the 27.12 MHz input signal is multiplied by the value

defined in PLLDiv_FB and divided by two, and the second stage divides this frequency by the value defined by

PLLDIV_Out.

Bit

Symbol

ClkOutSel

ClkOut_En

PLL_PD

PLLDiv_FB

Access

rights

r/w

Table 175. PLL_Ctrl register (address3Dh)

Bit

Symbol

Description

7 to 4

CLkOutSel

• 0h - pin CLKOUT is used as I/O

• 1h - pin CLKOUT shows the output of the analog PLL

• 2h - pin CLKOUT is hold on 0

• 3h - pin CLKOUT is hold on 1

• 4h - pin CLKOUT shows 27.12 MHz from the crystal

• 5h - pin CLKOUT shows 13.56 MHz derived from the crystal

• 6h - pin CLKOUT shows 6.78 MHz derived from the crystal

• 7h - pin CLKOUT shows 3.39 MHz derived from the crystal

• 8h - pin CLKOUT is toggled by the Timer0 overflow

• 9h - pin CLKOUT is toggled by the Timer1 overflow

• Ah - pin CLKOUT is toggled by the Timer2 overflow

• Bh - pin CLKOUT is toggled by the Timer3 overflow

• Ch...Fh - RFU

ClkOut_En

Enables the clock at Pin CLKOUT

PLL_PD

PLL power down

1-0

PLLDiv_FB

PLL feedback divider

Table 176. PLL_Ctrl register bits

CLRC663

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5.3 — 3 January 2024

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