CLRC663 datasheet(60/177 Pages) NXP

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NXP Semiconductors

CLRC663

High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus

9 CLRC663 registers

9.1 Register bit behavior

Depending on the functionality of a register, the access conditions to the register can vary. In principle, bits with

same behavior are grouped in common registers. The access conditions are described in the table below:

Abbreviation

Behavior

Description

r/w

read and write

These bits can be written and read via the host interface. Since they are used only

for control purposes, the content is not influenced by the state machines but can

be read by internal state machines.

dynamic

These bits can be written and read via the host interface. They can also be written

automatically by internal state machines, for example Command register changes

its value automatically after the execution of the command.

read only

These register bits indicate hold values which are determined by internal states

only.

write only

Reading these register bits always returns zero.

RFU

These bits are reserved for future use and must not be changed. In case of a

required write access, it is recommended to read out this bits, modify other bits of

the register and write back only the modified bits (read-modify-write).

Table 49. Behavior of register bits and their designation

Address

Function

00h

Command

Starts and stops command execution

01h

HostCtrl

Host control register

02h

FIFOControl

Control register of the FIFO

03h

WaterLevel

Level of the FIFO underflow and overflow warning

04h

FIFOLength

Length of the FIFO

05h

FIFOData

Data In/Out exchange register of FIFO buffer

06h

IRQ0

Interrupt register 0

07h

IRQ1

Interrupt register 1

08h

IRQ0En

Interrupt enable register 0

09h

IRQ1En

Interrupt enable register 1

0Ah

Error

Error bits showing the error status of the last command execution

0Bh

Status

Contains status of the communication

0Ch

RxBitCtrl

Control register for anticollision adjustments for bit oriented protocols

0Dh

RxColl

Collision position register

0Eh

TControl

Control of Timer 0..3

0Fh

T0Control

Control of Timer0

10h

T0ReloadHi

High register of the reload value of Timer0

11h

T0ReloadLo

Low register of the reload value of Timer0

Table 50. CLRC663 registers overview

CLRC663

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5.3 — 3 January 2024

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