CLRC663 datasheet(69/177 Pages) NXP

69 / 177 page

NXP Semiconductors

CLRC663

High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus

Bit

Symbol

Description

Timer4IRQEn

Set to logic 1, it allows the Timer4 interrupt request (indicated by the bit Timer4IRQ) to be

propagated to the GlobalIRQ

Timer3IRQEn

Set to logic 1, it allows the Timer3 interrupt request (indicated by the bit Timer3IRQ) to be

propagated to the GlobalIRQ

Timer2IRQEn

Set to logic 1, it allows the Timer2 interrupt request (indicated by the bit Timer2IRQ) to be

propagated to the GlobalIRQ

Timer1IRQEn

Set to logic 1, it allows the Timer1 interrupt request (indicated by the bit Timer1IRQ) to be

propagated to the GlobalIRQ

Timer0IRQEn

Set to logic 1, it allows the Timer0 interrupt request (indicated by the bit Timer0IRQ) to be

propagated to the GlobalIRQ

Table 70. IRQ1EN bits...continued

9.6 Contactless interface configuration registers

9.6.1 Error

Error register.

Bit

Symbol

EE_Err

FiFoWrErr

FIFOOvl

MinFrameErr

NoDataErr

CollDet

ProtErr

IntegErr

Access

rights

Table 71. Error register (address 0Ah)

Bit

Symbol

Description

EE_Err

An error appeared during the last EEPROM command. For

details see the descriptions of the EEPROM commands

FIFOWrErr

Data was written into the FIFO, during a transmission of a possible CRC, during "RxWait", "Wait

for data" or "Receiving" state, or during an authentication command. The Flag is cleared when a

new CL command is started. If RxMultiple is active, the flag is cleared after the error flags have

been written to the FIFO.

FIFOOvl

Data is written into the FIFO when it is already full. The data that is already in the FIFO remains

untouched. All data that is written to the FIFO after this Flag is set to 1 will be ignored.

Min

FrameErr

A valid SOF was received, but afterwards less than 4 bits of data were received.

Note: Frames with less than 4 bits of data are automatically discarded and the RxDecoder

stays enabled. Furthermore no RxIRQ is set. The same is valid for less than 3 bytes, if the EMD

suppression is activated

Note: MinFrameErr is automatically cleared at the start of a receive or transceive command. In

case of a transceive command, it is cleared at the start of the receiving phase ("Wait for data"

state)

NoDataErr

Data should be sent, but no data is in FIFO

CollDet

A collision has occurred. The position of the first collision is shown in the register RxColl.

Note: CollDet is automatically cleared at the start of a receive or transceive command. In case of

a transceive command, it is cleared at the start of the receiving phase ("Wait for data" state).

Note: If a collision is part of the defined EOF symbol, CollDet is not set to 1.

Table 72. Error bits

CLRC663

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5.3 — 3 January 2024

69 / 177

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