CLRC663 datasheet(52/177 Pages) NXP

52 / 177 page

NXP Semiconductors

CLRC663

High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus

Independent of the voltage it is recommended to buffer these supplies with blocking capacitances close to

the terminals of the package. VDD and PVDD are recommended to be blocked with a capacitor of 100 nF min,

TVDD is recommended to be blocked with 2 capacitors, 100 nF parallel to 1.0 μF

AVDD and DVDD are not supplied input pins. They are output pins and shall be connected to blocking

capacitors 470 nF each.

8.9.2 Power reduction mode

8.9.2.1 Power-down

A hard power-down is enabled with HIGH level on pin PDOWN. This turns off the internal 1.8 V voltage

regulators for the analog and digital core supply as well as the oscillator. All digital input buffers are separated

from the input pads and clamped internally (except pin PDOWN itself). The output pins are switched to high

impedance. HardPowerDown is performing a reset of the IC. All registers will be reset, the Fifo will be cleared.

To leave the power-down mode the level at the pin PDOWN as to be set to LOW. This starts the internal start-up

sequence.

8.9.2.2 Standby mode

The standby mode is entered immediately after setting the bit PowerDown in the register Command. All internal

current sinks are switched off. Voltage references and voltage regulators are set into standby mode.

In opposition to the power-down mode, the digital input buffers are not separated by the input pads and keep

their functionality. The digital output pins do not change their state.

During standby mode, all registers values, the FIFO’s content and the configuration itself keeps its current

content.

To leave the standby mode, the bit PowerDown in the register Command is cleared. This triggers the internal

start-up sequence. The reader IC is in full operation mode again when the internal start-up sequence is

finalized.

A value of 55h must be sent to the CLRC663 using the RS232 interface to leave the standby mode. This is must

at RS232, but cannot be used for the I2C/SPI interface. Then read accesses shall be performed at address 00h

until the device returns the content of this address. The return of the content of address 00h indicates that the

device is ready to receive further commands and the internal start-up sequence is finalized.

8.9.2.3 Modem off mode

When the ModemOff bit in the register Control is set the antenna transmitter and the receiver are switched off.

To leave the modem off mode, clears the ModemOff bit in the register Control.

8.9.3 Low-Power Card Detection (LPCD)

The low-power card detection is an energy saving mode in which the CLRC663 is not fully powered

permanently.

The LPCD works in two phases. First the standby phase is controlled by the wake-up counter (WUC),

which defines the duration of the standby of the CLRC663. Second phase is the detection-phase. In this

phase, the values of the I and Q channel are detected and stored in the register map. (LPCD_I_Result,

LPCD_Q_Result).This time period can be handled with Timer3. The value is compared with the min/max values

in the registers (LPCD_IMin, LPCD_IMax; LPCD_QMin, LPCD_QMax). If it exceeds the limits, an LPCDIRQ is

raised.

CLRC663

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5.3 — 3 January 2024

52 / 177

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