CLRC663 datasheet(42/177 Pages) NXP

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NXP Semiconductors

CLRC663

High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus

001aan358

13.56 MHz

I/O CLOCK

GENERATION

I-clks

Q-clks

clk_27 MHz

TIMING

GENERATION

ADC

DATA

Adc_data_ready

clk_27 MHz

mixer

mix_out_i_p

2-stage BBA

mix_out_i_n

out_i_p

out_i_n

rx_p

rx_n

rx_p

rx_n

mixer

mix_out_q_p

2-stage BBA

mix_out_q_n

out_q_p

out_q_n

rcv_gain<1:0>

rcv_hpcf<1:0>

fully/quasi-differential

rcv_gain<1:0>

rcv_hpcf<1:0>

rx_p

rx_n

Figure 28. Block diagram of receiver circuitry

The receiver can also be operated in a single ended mode. In this case, the Rcv_RX_single bit has to be set. In

the single ended mode, the two receiver pins RXP and RXN need to be connected together and will provide a

single ended signal to the receiver circuitry.

When using the receiver in a single ended mode, the receiver sensitivity is decreased and the achievable

reading distance might be reduced, compared to the fully differential mode.

Mode

rcv_rx_single

pins RXP and RXN

Fully differential

provide differential signal from differential antenna by separate rx-

coupling branches

Quasi differential

connect RXP and RXN together and provide single ended signal from

antenna by a single rx-coupling branch

Table 32. Configuration for single or differential receiver

The quadrature-demodulator uses two different clocks, Q-clock and I-clock, with a phase shift of 90° between

them. Both resulting baseband signals are amplified, filtered, digitized and forwarded to a correlation circuitry.

The typical application is intended to implement the Fully differential mode and will deliver maximum reader/

writer distance. The Quasi differential mode can be used together with dedicated antenna topologies that allow

a reduction of matching components at the cost of overall reading performance.

During low-power card detection the DC levels at the I- and Q-channel mixer outputs are evaluated. This

requires that mixers are directly connected to the ADC. This can be configured by setting the bit Rx_ADCmode

in register Rcv (38h).

8.6.4 Active antenna concept

Two main blocks are implemented in the CLRC663. A digital circuitry, comprising state machines, coder and

decoder logic and an analog circuitry with the modulator and antenna drivers, receiver and amplification

circuitry. For example, the interface between these two blocks can be configured in the way, that the interfacing

signals may be routed to the pins SIGIN and SIGOUT. The most important use of this topology is the active

antenna concept where the digital and the analog blocks are separated. This opens the possibility to connect

e.g. an additional digital block of another CLRC663 device with a single analog antenna frontend.

CLRC663

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5.3 — 3 January 2024

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