CLRC663 datasheet(92/177 Pages) NXP

92 / 177 page

NXP Semiconductors

CLRC663

High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus

Bit

Symbol

MinLevel

MinLevelP

Access

rights

r/w

Table 163. RxThreshold register (address 37h)

Bit

Symbol

Description

7 to 4

MinLevel

Defines the MinLevel of the reception.

Note: The MinLevel should be higher than the noise level in the system.

3 to 0

MinLevelP

Defines the MinLevel of the phase shift detector unit.

Table 164. RxThreshold bits

9.12.5 Rcv

Bit

Symbol

Rcv_Rx_single

Rx_ADCmode

SigInSel

RFU

CollLevel

Access

rights

r/w

Table 165. Rcv register (address 38h)

Bit

Symbol

Description

Rcv_Rx_single

Single RXP Input Pin Mode;

0: Fully Differential

1: Quasi-Differential

Rx_ADCmode

Defines the operation mode of the Analog Digital Converter (ADC)

0: normal reception mode for ADC

1: LPCD mode for ADC

5 to 4

SigInSel

Defines input for the signal processing unit:

0h - idle

1h - internal analog block (RX)

2h - signal in over envelope (ISO/IEC14443A)

3h - signal in over s3c-generic

3 to 2

RFU

1 to 0

CollLevel

Defines the strength of a signal to be interpreted as a collision:

0h - Collision has at least 1/8 of signal strength

1h - Collision has at least 1/4 of signal strength

2h - Collision has at least 1/2 of signal strength

3h - Collision detection is switched off

Table 166. Rcv bits

9.12.6 RxAna

This register allows setting the gain (rcv_gain) and high pass corner frequencies (rcv_hpcf).

CLRC663

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Product data sheet

Rev. 5.3 — 3 January 2024

92 / 177

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