the secondary device transmits the least significant byte (LSB). The main device may or may not acknowledge

receipt of the second data byte. The main device can end the data transfer by generating a Not-Acknowledge

after receiving any data byte, or generating a start or stop condition. Continually sending the register pointer

bytes is not necessary if repeated reads from the same register are desired. The device retains the register

pointer value until the value is changed by the next write operation.

Figure 7-11 shows the write operation timing diagram. Figure 7-12 shows the read operation timing diagram. The

following diagrams show reading and writing to 16-bit registers.

Register bytes are sent by most significant byte first, followed by the least significant byte.

Frame 1 Two-Wire Target Address Byte

Frame 2 Register Pointer Byte

Start By

Main

ACK By

Secondary

ACK By

Secondary

1

9

1

ACK By

Secondary

1

D15 D14

D13

D12 D11 D10

D9

D8

9

9

SDA

SCL

1

0

0

A1

A0

R/W

P7

P6

P5

P4

P3

P2

P1

P0

Frame 4 Data LSByte

Frame 3 Data MSByte

ACK By

Secondary

Stop By

Main

1

D7

D6

D5

D4

D3

D2

D1

D0

9

0

0

1

A.

The value of the Secondary Device Address byte is determined by the settings of the A0 address pin. See Table 7-2.

B.

The device does not support packet error checking (PEC) or perform clock stretching.

Figure 7-11. Timing Diagram for Write Word Format

Frame 1 Two-Wire Secondary Address Byte

Frame 2 Data MSByte

1

Start By

Main

ACK By

Secondary

ACK By

Main

From

Secondary

1

9

1

9

SDA

SCL

0

0

A3

R/W

D15 D14 D13

D12

D11 D10

D9

D8

A2

A1

A0

Frame 3 Data LSByte

Stop

No ACK By

Main

From

Secondary

1

9

D7

D6

D5

D4

D3

D2

D1

D0

0

1

A.

The value of the Secondary Device Address byte is determined by the settings of the A0 address pin. See Table 7-2.

B.

Read data is from the last register pointer location. If a new register is desired, the register pointer must be updated. See Figure 7-13.

C.

ACK by the main device can also be sent.

D.

The device does not support packet error checking (PEC) or perform clock stretching.

Figure 7-12. Timing Diagram for Read Word Format

Frame 1 Two-Wire Secondary Address Byte

Frame 2 Register Pointer Byte

1

Start By

Main

ACK By

Secondary

ACK By

Secondary

1

9

1

9

SDA

SCL

0

0

A1

A0

R/W

P7

P6

P5

P4

P3

P2

P1

P0

Stop

1

0

A.

The value of the Secondary Device Address Byte is determined by the settings of the A0 address pin. See Table 7-2.

Figure 7-13. Typical Register Pointer Set

7.5.1.2 High-Speed I2C Mode

When the bus is idle, both the SDA and SCL lines are pulled high by the pullup resistors. The main device

generates a start condition followed by a valid serial byte containing high-speed (HS) main device code

00001XXX. This transmission is made in fast (400 kHz) or standard (100 kHz) (F/S) mode at no more than 400

kHz. The device does not acknowledge the HS main device code, but does recognize the code and switches

internal filters of the device to support 2.94-MHz operation.

INA700

SBOSAB4A – MAY 2023 – REVISED SEPTEMBER 2023

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