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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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UPD17062 датащи(PDF) 105 Page - Renesas Technology Corp |
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UPD17062 датащи(HTML) 105 Page - Renesas Technology Corp |
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105 / 298 page  103 µPD17062 10.5.7 PLL Data Register Fig. 10-10 shows how the PLL data register functions. The PLL data register sets the frequency division ratio of the PLL frequency synthesizer. For the pulse swallow method, all 16 bits are valid, the 12 high-order bits are set in the program counter, and the remaining four low-order bits are set in the swallow counter. Fig. 10-10 PLL Data Register DBF3 0CH DBF2 0DH DBF1 0EH DBF0 0FH b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 PLLR 41H PLL frequency synthesizer frequency division ratio 16 b15 b14 b13 b12 b11 b10 b9 b8 256 (0100H) x 0 (0000H) 2 16 - 1 (0FFFFH) Not to be set. Frequency division ratio N:N = x PLL frequency synthesizer Symbol Peripheral address Peripheral hardware Name Data buffer Symbol Address Bit Data Transfer data GET PUT Name PLLR data register Peripheral register Valid data |
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