UPD17062 datasheet(72/298 Pages) RENESAS

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µPD17062

Table 9-1

Peripheral Hardware Control Functions of Control Registers (1/5)

Remark *: Retains the previous state.

Control register

Peripheral hardware control function

At reset

Ad-

dress

Read/

write

Symbol

Function outline

Set value

Stack pointer

(SP)

01H

R/W

(SP2)

(SP1)

(SP0)

Fixed at 0

Stack pointer

(3 bits are valid.)

BTM0ZX

On/off of zerocross circuit

BTM0CK2

BTM0CK0

BTM0CY

INTVSYN

INTNC

INTNCMD2

INTNCMD1

INTNCMD0

09H

R/W

17H

0FH

15H

R/W

Timer 0

clock select

BTM0CK1

Basic timer 0

carry flip-flop

judge register

Interrupt-level

judge register

INTNC mode

select register

Base clock setting of basic

timer 0 (internal/external)

Fixed at 0

Detects the carry flip-flop state

Fixed at 0

Detects the VSYNC pin state

Fixed at 0

Detects the INTNC pin state

Fixed at 0

Selects the pulse width of

interrupt accept pulse width

of the INTNC pin

No operation

Operation

Pulse for timer carry flop-flop set

0: 10 Hz (100 ms, internal)

1: 200 Hz (5 ms, internal)

2: 10 Hz (100 ms, internal)

3: 200 Hz (5 ms, internal)

4: fTMIN/5 Hz (external)

5: 200 Hz (5 ms, internal)

6: fTMIN/6 Hz (external)

7: 200 Hz (5 ms, internal)

Pulse for timer interrupt

0: 200 Hz (5 ms, internal)

1: 10 Hz (100 ms, internal)

2: 50 Hz (20 ms, internal)

3: 50 Hz (20 ms, internal)

4: 200 Hz (5 ms, internal)

5: fTMIN/5 Hz (external)

6: 200 Hz (5 ms, internal)

7: fTMIN/6 Hz (external)

00*

011

000

Reset

Set

Low level

High level

Low level

High level

0: Accepts with edge

1: 200

s 2: 400 s 3: 2 ms

4: 4 ms

µµ

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