UPD17062 datasheet(14/298 Pages) RENESAS

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µPD17062

Pin No.

DIP QFP

(GC)

Symbol

Description

Output type

At power-on reset

P1A3

P1A0

P1B3

P1B0

RED

GREEN

BLUE

BLANK

HSYNC

VSYNC

P1C3/ADC1

P1C2

P1C1

ADC0

P0B3/HSCNT

P0B2/TMIN

P0B1

P0B0/SI

P0A3/SO

P0A2/SCK

P0A1/SCL

P0A0/SDA

4-bit output port. This N-ch open-drain output

port has an intermediate withstand voltage.

4-bit I/O port. Each bit can be set for input or

output.

Outputs the character data corresponding to R, G,

and B of the IDC display. The output is active-

high.

Outputs the blanking signal for cutting the

video signal of the IDC display. The output is

active-high.

Inputs the horizontal synchronizing signal of the

IDC display. The input must be active-low.

Inputs the vertical synchronizing signal of the IDC

display. The input must be active-low. The input

signal can generate an interrupt.

Input of port 1C and A/D converter

• P1C3 to P1C1

3-bit I/O port

• ADC1

Input of a 4-bit A/D converter

Serial interface and input for port 0B, port 0A,

horizontal synchronizing signal counter, and

timer

• P0A3 to P0A0

4-bit I/O port. Each bit can be set for input or

output.

• P0B3 to P0B0

4-bit I/O port. Each bit can be set for input or

output.

• HSCNT

Inputs the count of the horizontal

synchronizing signal. The input is self-

biased.

• TMIN

Timer input. The pin inputs the commercial

power to be used for the clock.

• SI, SO, SCK

Input/output for the three-wire serial interface

• SI: Serial data input

• SO: Serial data output

• SCK: Shift clock input/output

• SDA, SCL

Input/output for the two-wire serial interface

• SCL: Serial clock input/output

• SDA: Serial data input/output

N-ch open-drain

CMOS push-pull

—

CMOS push-pull

—

N-ch open-drain

(P0A1, P0A0)

CMOS push-pull

(Other than P0A1

or P0A0)

Undefined

Input

Low level

Input

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