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UPD17062 датащи(PDF) 73 Page - Renesas Technology Corp

номер детали UPD17062
подробное описание детали  MOS INTEGRATED CIRCUIT
PDF  298 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD17062 датащи(HTML) 73 Page - Renesas Technology Corp

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µPD17062
Table 9-1
Peripheral Hardware Control Functions of Control Registers (2/5)
Remark
*: Retains the previous state.
Control register
Peripheral hardware control function
At reset
Register
Ad-
dress
Read/
write
b3
b2
b1
b0
Symbol
Function outline
Set value
01
P
o
w
e
r
O
n
S
T
O
P
C
E
Interrupt edge
select register
Interrupt
permission
register
Interrupt
request
register
CE pin level
judge register
PLL reference
clock select
register
PLL unlock
flip-flop judge
register
PLL unlock
flip-flop
sensibility
select register
1FH
R/W
2FH
R/W
3FH
R
07H
R
13H
R/W
22H
R
32H
R/W
0
IEGVSYN
0
IEGNC
IPVSYN
IPSIO0
IPBTM0
IPNC
IRQVSYN
IRQSIO0
IRQBTM0
IRQNC
0
0
0
CE
PLLRFCK3
PLLRFCK2
PLLRFCK1
PLLRFCK0
0
0
0
PLLUL
0
0
PLULSEN1
PLULSEN0
Fixed at 0
Sets the interrupt issue edge (VSYNC)
Fixed at 0
Sets the interrupt issue edge (INTNC)
- Serial interface 0
- VSYNC signal
- Basic timer 0
- INTNC pin
- Serial interface 0
- VSYNC signal
- Basic timer 0
- INTNC pin
Sets
the in-
terrupt
permis-
sion of:
Sets
the in-
terrupt
request
of:
Fixed at 0
Detects the CE pin state
Fixed at 1
Fixed at 0
Detects the unlock flip-flop state
Fixed at 0
Sets the set delay time for
the unlock flip-flop
Rising edge
Falling edge
Rising edge
Falling edge
00
0
01
1
Interrupt
disabled
Interrupt
enabled
No interrupt
request/
processing
in progress
Interrupt
request made
00
0
Low level
High Level
0–
2: 6.25 kHz
3: 12.5 kHz
6: 25 kHz
F: Operation stopped (disabled state)
0, 1, 4, 5, 7-E: Setting disabled
Locked state
Unlocked state
00
1
1
01
0
1
1.25
3.5
0.25
1.5 s
3.75 s
0.5 s
µµ
µ
Disabled
state
to
to
to
FF
*
0*
*
00
*



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