UPD17062 datasheet(9/298 Pages) RENESAS

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µPD17062

8.5

INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MP) ......................

8.6

GENERAL-PURPOSE REGISTER POINTER (RP) ..........................................................................

8.7

PROGRAM STATUS WORD (PSWORD) ......................................................................................

REGISTER FILE (RF) ...................................................................................................................

9.1

IDCDMAEN (00H, b1) ......................................................................................................................

9.2

SP (01H) ...........................................................................................................................................

9.3

CE (07H, b0) .....................................................................................................................................

9.4

SERIAL INTERFACE MODE REGISTER (08H) ..............................................................................

9.5

BTM0MD (09H) ...............................................................................................................................

9.6

INTVSYN (0FH, b2) .........................................................................................................................

9.7

INTNC (0FH, b0) ..............................................................................................................................

9.8

HORIZONTAL SYNCHRONIZING SIGNAL COUNTER CONTROL (11H, 12H) ..........................

9.9

PLL REFERENCE MODE SELECTION REGISTER (13H) ..............................................................

9.10

SETTING OF INTNC PIN ACCEPTANCE PULSE WIDTH (15H) ..................................................

9.11

TIMER CARRY (17H) .......................................................................................................................

9.12

SERIAL INTERFACE WAIT CONTROL (18H) ................................................................................

9.13

IEGNC (1FH) ....................................................................................................................................

9.14

A/D CONVERTOR CONTROL (21H) ..............................................................................................

9.15

PLL UNLOCK FLIP-FLOP JUDGE REGISTER (22H) .....................................................................

9.16

PORT1C I/O SETTING (27H) ..........................................................................................................

9.17

SERIAL I/O0 STATUS REGISTER (28H) .......................................................................................

9.18

INTERRUPT PERMISSION FLAG (2FH) ........................................................................................

9.19

CROM BANK SELECTION (30H) ...................................................................................................

9.20

IDCEN (31H) ....................................................................................................................................

9.21

PLL UNLOCK FLIP-FLOP DELAY CONTROL REGISTER (32H) ..................................................

9.22

P1BBIOn (35H) ................................................................................................................................85

9.23

P0BBIOn (36H) ................................................................................................................................85

9.24

P0ABIOn (37H) ................................................................................................................................86

9.25

SETTING OF INTERRUPT REQUEST GENERATION TIMING IN

SERIAL INTERFACE MODE (38H) .................................................................................................

9.26

SHIFT CLOCK FREQUENCY SETTING (39H) ...............................................................................

9.27

IRQNC (3FH) ....................................................................................................................................

10. DATA BUFFER (DBF) ..................................................................................................................

10.1

DATA BUFFER STRUCTURE .........................................................................................................

10.2

FUNCTIONS OF DATA BUFFER ....................................................................................................

10.3

DATA BUFFER AND TABLE REFERENCING ................................................................................

10.4

DATA BUFFER AND PERIPHERAL HARDWARE .........................................................................

10.5

DATA BUFFER AND PERIPHERAL REGISTERS ..........................................................................

10.6

PRECAUTIONS WHEN USING DATA BUFFERS .........................................................................

104

11. INTERRUPT ................................................................................................................................. 106

11.1

INTERRUPT BLOCK CONFIGURATION ........................................................................................

106

11.2

INTERRUPT FUNCTION ................................................................................................................. 108

11.3

INTERRUPT ACCEPTANCE ............................................................................................................ 111

11.4

OPERATIONS AFTER INTERRUPT ACCEPTANCE ...................................................................... 116

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