ZAMC4100 datasheet(98/156 Pages) RENESAS

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ZAMC4100 Datasheet

January 26, 2016

Table 3.47 LINCTRL Registers Bits Description

Bit Description

LINWUMD: LIN wake-up detection mode (see Figure 3.27).

1 = LIN wake-up is detected if there is a falling edge at the LIN pin followed by a dominant state longer

than tLINWU and a rising edge at the LIN pin.

0 = LIN wake-up is detected if there is a falling edge at the LIN pin followed a by dominant state > tLINWU.

2:1

LINSHDB: LIN short de-bounce time configuration.

00 = LIN short is detected if it is longer than 96 cycles of OSCH/5 clock.

01 = LIN short is detected if it is longer than 128 cycles of OSCH/5 clock.

10 = LIN short is detected if it is longer than 192 cycles of OSCH/5 clock.

11 = LIN short is detected if it is longer than 255 cycles of OSCH/5 clock.

LINFAST: LIN fast mode enable bit.

1 = Fast mode is enabled.

0 = Fast mode is disabled.

Table 3.48 LINSTAT Register Bits Mapping

Name

LINSTAT

Bit No

Bit name

Reset

Access

R/W

Address

0x18

R/W = Read/Write ‘1’ bit; U = Unimplemented, read as ‘0’

Table 3.49 LINSTAT Register Bits Mapping

Bit Description

LINSHIF: LIN short interrupt flag.

1 = LIN short has been detected, and the transmitter is disabled.

0 = LIN short has not been detected.

LINDTOIF: LIN dominant time-out interrupt flag.

1 = Dominant time-out has been detected, and the transmitter is disabled.

0 = Dominant time-out has not been detected.

LINWUIF: LIN wake-up interrupt flag.

1 = Wake-up event has been detected on the LIN bus; i.e., the transition from SLEEP to NORMAL Mode is

caused by the LIN bus.

0 = Wake-up event has not been detected on the LIN bus; i.e. any transition from SLEEP to NORMAL

Mode has been caused by the WDT (see section 3.5.4).

Note: All LIN interrupt flags are cleared by writing ‘1’ in the corresponding LINSTAT bit.

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