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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ZAMC4100 датащи(PDF) 60 Page - Renesas Technology Corp |
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ZAMC4100 датащи(HTML) 60 Page - Renesas Technology Corp |
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60 / 156 page  ZAMC4100 Datasheet © 2016 Integrated Device Technology, Inc. 60 January 26, 2016 3.8.1. Half-Bridge Drivers Control and Status Register All half-bridge drivers are enabled and disabled using the HBDCTRL register. The bit mapping of HBDCTRL is given in Table 3.13, and the bit descriptions are in Table 3.14. The over-current and diagnostic status bits are allocated in register HBDSTAT, which is described in Table 3.15 and Table 3.16. Table 3.13 HBDCTRL Register Bits Mapping Name HBDCTRL Bit No 7 6 5 4 3 2 1 0 Bit name Reset 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Address 0x06 R/W = Read/Write Table 3.14 HBDCTRL Bits Description Bit Description 7,5,3,1 HBxHEN: 1), 2), 3), 4) High-side MOSFET enable bit for half-bridge driver x, (x=4 to 1) 1 = High-side MOSFET enabled 0 = High-side MOSFET disabled 6,4,2,0 HBxLEN: 1), 2), 3), 4) Low-side MOSFET enable bit for half-bridge driver x, (x=4 to 1) 1 = Low-side MOSFET enabled 0 = Low-side MOSFET disabled 1) When both enable bits of one driver are set or cleared (for example, HB1HEN = 1 and HB1LEN = 1 or HB1HEN = 0 and HB1LEN = 0), the driver is disabled. 2) Bits HBxHEN and HBxLEN are automatically cleared upon entry into SLEEP or STANDBY Mode. 3) These bits are automatically cleared if there is an over-temperature event. 4) These bits are gated if a failure event (OVT, OC, OV, UV, or CPVE) is detected, and a corresponding interrupt flag is set (see Figure 3.12). |
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