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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ZAMC4100 датащи(PDF) 87 Page - Renesas Technology Corp |
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ZAMC4100 датащи(HTML) 87 Page - Renesas Technology Corp |
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87 / 156 page  ZAMC4100 Datasheet © 2016 Integrated Device Technology, Inc. 87 January 26, 2016 Table 3.39 ADCSTAT Register Bits Mapping Name ADCSTAT Bit No 7 6 5 4 3 2 1 0 Bit name Reset U U U U U U 0 0 Access U U U U U U R/Wc R/Wc Address 0x0D R/Wc = Read/Write 1 to clear, U = Unimplemented, read as ‘0’ Note: When the comparator is enabled (bit CMPEN = ‘1’), the ADCRDYIF flag bit is automatically masked. As a result, the global ADC interrupt (see Figure 3.8) is not generated at the end of each conversion cycle; it is generated only when a valid comparator event is detected. Table 3.40 ADCSTAT Register Bits Description Bit Description 7:2 Unimplemented bits. Read as 0. 1 ADCCMPIF: ADC comparator counter interrupt flag. 1 = Compare counter (CMP) matches the value programmed in reference RCMPCNT register (Table 3.50). 0 = There is no result matching detected by comparator counter. 0 ADCRDYIF: ADC ready interrupt flag. 1 = Current ADC conversion has finished and ADCRESx (Table 3.50) contains results ready to be read by the MCU. 0 = ADC conversion has not finished and/or the result has not been read from the ADCRESX register. Note: If CMPEN is set, this flag is masked; see Table 3.42. |
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