ZAMC4100 datasheet(55/156 Pages) RENESAS

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ZAMC4100 Datasheet

January 26, 2016

3.7.1.

SBC and MCU SPI Connection Principles

The SBC to MCU connections using the SPI bus are shown in Figure 3.9. The SPI line definitions are given in

Table 3.11.

Figure 3.9 MCU-to-SBC Connection via SPI

SBC

MOSI

MISO

SPI_CLK

CSN

MCU

SPI Slave

SPI Master

Interrupt

Logic

IRQN

IRQ0

IRQ1

IRQn

Processor

Core

SBC

Registers

ZAMC4100

wr_en

rd_en

Table 3.11 SPI Lines Description

Line Name

Description

CSN

Active-low chip select with an internal pull-up in the SBC. The falling edge of the CSN line

initiates the SPI data transfer. A high level on CSN disables the SPI of SBC.

MOSI

Master-Out Slave-In. The SBC has an internal pull-down resistor.

MISO

Master-In Slave-Out.

SPI_CLK

SPI clock with an internal pull-up in the SBC. In inactive state, the SPI_CLK line is in high. The

value on the MISO and MOSI lines is changed on the falling edge of SPI_CLK and captured on

the rising edge of SPI_CLK.

The SPI slave recognizes two frames: the data WRITE frame and the data READ frame (see Figure 3.10).

The SPI communication starts when the MCU switches the CSN line to LOW and ends when the CSN line goes

HIGH. Each SPI frame begins with a command byte followed by the data byte(s).

The SPI command frame (Figure 3.10–C) contains the R/

W bit for indicating the access type, five address bits

for pointing to the accessed SBC register, and the B bit for enabling the burst read mode.

As the command byte is shifted in, the SBC automatically shifts out the slave status byte containing the important

interrupt status bits (Figure 3.10–D).

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