STWBC2-HP datasheet(36/96 Pages) STMICROELECTRONICS

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Figure 39. QF block diagram overview

Note that by default the QF circuit is configured with the PLL source clock.

2.2.3.3.1

Digital FSM

The digital machine includes the asynchronous RS path to close the loop with the analog cell.

The controller uses 12bits counters to process the blank time, the time-out and to evaluate the ringing half-period.

The cycle_time output is the sum of two consecutive half-period durations so that the full period of ring is

available.

The digital machine is clocked with the PLL by default to get enough timing resolution of the ringing period. It can

be also clocked by the AFE clock to reduce current consumption accepting a lower timing resolution.

2.2.3.3.2

Startup oscillation

The QF controller drives the current generator synchronously with the tank zero cross. Hence, the QF controller

and the LC tank form an oscillator where the LC tank contributes to the loop delay. However, at startup, the LC

tank is not yet ringing so that no zero cross event can happen to synchronize the controller. By default, the current

generator polarity is reverted when the time-out time is reached. By consequence, at startup, the QF controller

drives the tank at an effective period of 2 times the time-out value. This period represents the effective start-up

period.

2.2.3.3.3

Spread functionality

If the start-up period is far away from the resonating point of the LC tank or if the tank is very selective, the LC

oscillation is small. Considering some offset in the zero-cross comparator, these oscillations can be small enough

so that they never trig the comparator. If this happens, the system does not run an oscillator mode and stays at

the start-up period.

To avoid this situation, the QF controller integrates a spread function that can be enabled independently. When

the QF system is not locked in oscillator mode, the spread function changes the effective time-out time at each

loop of the state machine.

The effective time-out is incremented from blanking-time value to the programmed time-out value by 1/8 steps (so

each step is (time-out – blanking-time)/8).

This time-out variation allows exciting the LC tank with a variable frequency and a variable duty cycle. By

consequence, the LC tank excitation could come to be closer to the resonant frequency. Then, the ring voltage

enlarges enough to pass the zero-cross comparator threshold and the system can expect to lock in oscillator

mode.

The QF controller reports a locked status information. Locked status bit is set if the controller detects a zero-cross

happening before the time-out. If the time-out occurs, the locked bit is cleared.

The blanking time and time-out values can be freely modified when the QF controller is disabled. When QF

controller is running, the values are synchronized using an update bit present in the registers.

STWBC2-HP

Digital AFE functions

DS13825 - Rev 1.0

page 36/96

STWBC2-HP датащи(PDF) 36 Page - STMicroelectronics