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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STWBC2-HP датащи(PDF) 60 Page - STMicroelectronics |
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STWBC2-HP датащи(HTML) 60 Page - STMicroelectronics |
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60 / 96 page  2.2.11.3.3 NVM commands overview The NVM controller allows configuring all user command operations on the NVM_OP_REG[3:0] signals with codes comprised between 0x0 up to 0x6; all the other commands are provided in test mode by the ATE tester equipment driving directly the NVM memory exposed pins during the EWS and FT. Table 44. NVM memory command overview Operation OP_REG[3:0] Description Standby 0x0 No operation Read Memory 0x1 Read memory data Soft-Program 0x2 Soft program selected sector Erase 0x3 Erase selected sector Word Program 0x4 Program Word selected sector Write Data on PL 0x5 Write Pre-Load data Read PL data 0x6 Read Pre-Load data FDMA direct 0x8 Read single ended mode – direct cell FDMA complementary 0x9 Read single ended mode – comp. cell DMA direct 0xA Direct Memory Access – direct cell DMA complementary 0xB Direct Memory Access – comp cell Write TOP_REG 0xC Write Test Operation Register Read TOP_REG 0xD Read Test Operation Register Read complementary PL 0xE Read Pre-Load complementary data 2.2.11.4 Programming 2.2.11.4.1 SW access The NVM memory access requires the following program sequences: • Evaluate that there is no NVM pending command by checking the NVM_BUSY bit of the NVM_CTRL_0 register (the bit must be cleared); wait until NVM_BUSY bit is cleared before moving to the next step. • Configure the memory operation command and the sector number respectively in the NVM_OP_REG and the NVM_SECT_SEL fields of the NVM_CTRL_1 register. • Select the NVM memory access request by setting the NVM_PC_REQ wc-bit field of register NVM_CTRL_0. • Waiting for the command completion notified by the NVM_EOC; if the on-going operation was a read command the return data may read back from the NVM_DATA_0 to 7 registers. In case of abort notified by NVM_ABRT bit field (this event should be avoided thanks to the SW interlock procedures described in the first step) the entire command sequence has to be reiterated. • Reset the NVM status bit by setting the NVM_STS_CLR wc bit field of register NVM_CTRL_0. • To deeply reduce the power consumption, the NVM should be disabled (power down) after reading the manufacturing parameters in functional mode. 2.2.11.4.2 HW access The sector-0 of NVM which stores the trimming data parameters is uploaded automatically from HW either following the reset sequence or by setting the NVM_HW_REQ command bit. During the NVM access the trimming data are written by HW. Here below follows the related program sequences: • Evaluate that there is no NVM pending command by checking the NVM_BUSY bit of the NVM_CTRL_0 register (the bit must be cleared); wait until NVM_BUSY bit is cleared before moving to the next step. • Configure the memory operation command and the sector number respectively in the NVM_OP_REG and the NVM_SECT_SEL fields of the NVM_CTRL_1 register selecting the sector-0 “000” and command memory read “0x1”. STWBC2-HP Digital AFE functions DS13825 - Rev 1.0 page 60/96 |
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