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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STWBC2-HP датащи(PDF) 66 Page - STMicroelectronics |
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STWBC2-HP датащи(HTML) 66 Page - STMicroelectronics |
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66 / 96 page  Figure 64. SPI block diagram overview 2.2.13.2 Feature list • Slave 16bits serial interface to master parallel peripheral bus • Complete asynchronous link between the SPI and PB bus • Clock ratio of spi_clk vs afe_clk is 2 • Supports multi-byte read and write with fixed, auto-increment or explicit address • Supports read-modify-write atomic sequence • Serial data order from MSB to LSB • Disable synchronizer stages in ATE test mode 2.2.13.3 Functional description The cell has 2 separate clock domains: Figure 65. SPI clock domain overview • The spi_clk domain contains the serial engine. It is reset with resetn and partially also with spi_csn. • The clk domain generates parallel peripheral bus access corresponding to the SPI transaction. The spi_clk domain serializer/deserializer is reset with spi_csn at 1. Hence, the machine restarts from scratch at each new SPI access. The serial machine is clocked on neg edge of spi_clk. During the SPI transaction, the machine decodes the access direction, the access address and the eventual write data. STWBC2-HP Digital AFE functions DS13825 - Rev 1.0 page 66/96 |
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