STWBC2-HP datasheet(52/96 Pages) STMICROELECTRONICS

52 / 96 page

During the DC-DC operation, the DCDC_STATUS register reports the status of the controller. If the BB-DCDC

detects a hard error (overload), the DCDC_ERROR bit is set to 1 and the BB-DCDC stops its operation

immediately. To restart the BB-DCDC, disable it by clearing the ENABLE bit in the DCDC_CTRL register and

enable it again.

2.2.7.17

Configuration register overview

For the BB-DCDC complete configuration registers overview please contact our sales representative.

2.2.8

VDoubler

2.2.8.1

Overview

The voltage doubler provides approximatively twice the buck DC-DC voltage to power the gate drivers. The digital

part is a simple programmable clock source.

2.2.8.2

Feature list

•

Provide clock to the analog power buffer

•

Select base clock from AFE main clock or PLL

2.2.8.3

Functional description

The VDoubler digital module is simply providing a configurable clock to the analog cell. The analog cell buffers

this clock with anti-cross-conduction circuit. By using external diodes and capacitor, the buck DC-DC voltage is

approximatively doubled.

Figure 53 shows the internal circuit block diagram

Figure 53. VDoubler block diagram overview

2.2.8.4

Programming

The VDoubler circuit requires the following program sequences:

•

If the Vdoubler circuit is enabled disable this by clearing the V_DOUBLER register.

•

Configure the constant division from 2 to 255 in the V_DOUBLER_CLK register.

•

Configure the clock source operation through the CLK_SEL bit field of the V_DOUBLER register.

•

Enable the Vdoubler circuit by setting the ENABLE bit field of the V_DOUBLER register.

Note that any constant division update or change of frequency requires the iteration of the above procedures.

2.2.8.5

Operating parameters

Table 37 summarizes the IP functional operating parameters

Table 37. VDoubler operating parameters

Parameter

Value

Operating frequency

16 MHz or 40 MHz

STWBC2-HP

Digital AFE functions

DS13825 - Rev 1.0

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